Reordering Buffer for Data Input Output Unit Parallel Processing
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Solution Overview
Problem
The existing data transmission methods between a digital signal processor (DSP) core and external memory or hardware often result in performance bottlenecks due to high data transmission cycles, and software pipelining without considering dependencies between FIFO operations can lead to inefficient parallel processing.
Innovation Solution
A data input/output unit with a FIFO memory and a reordering buffer that stores and outputs data in sequence based on a control signal, reducing data transmission cycles and enhancing parallel processing efficiency by adjusting the order of data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software pipelining is performed without considering the dependency between pop and push operations, then the number of commands processed in parallel increases and performance is enhanced, but the order of accessing the FIFO memory is reversed
Solution Approach 1:
A reordering buffer is introduced as an intermediary component between the FIFO memory and the processor. This buffer temporarily stores data and reorders it according to the correct sequence, allowing parallel processing of pop and push operations while ensuring that data is output in the proper FIFO order. The reordering buffer acts as a mediator that decouples the parallel operation capability from the sequential access requirement.
2Productivity
If data transmission cycles are reduced by using FIFO memory, then performance is enhanced, but the system requires precise coordination of data input/output timing
Solution Approach 1:
Data is pre-loaded into the FIFO memory in advance before the processor needs it. The FIFO memory continuously requests and stores data from external sources, so when the processor requires data, it is already available in the buffer. This preliminary action eliminates waiting time and reduces data transmission cycles, improving overall system performance.
3Productivity
If the FIFO memory continuously requests and stores data, then data transmission cycles are reduced, but the system requires additional buffer memory resources
Solution Approach 1:
The buffer memory is segmented into multiple regions: the FIFO memory region and the reordering buffer region. Each region serves a specific function - the FIFO memory handles continuous data pre-loading, while the reordering buffer manages the resequencing of data. This segmentation allows efficient parallel operations while optimizing memory resource utilization by assigning specific roles to different memory segments.
Data Source
AI summary
A data input/output unit is provided. The data input/output unit which is connected to a processor, and receives and outputs data in sequence based on a first schedule includes a first input first output (FIFO) memory connected to an external unit and the processor; and a reordering buffer connected to one side of the FIFO memory, and store data outputted from, or inputted to, the FIFO memory in a plurality of buffer regions in sequence, and output data stored in one of the plurality of buffer regions based on a control signal provided from the processor.