Repair Analysis Circuit for Memory Fail Address Storage
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Solution Overview
Problem
The increasing complexity of memory chip fabrication makes it difficult to produce chips with no defective cells, necessitating the use of redundancy memory to repair defective cells, which requires efficient detection and storage of fail addresses.
Innovation Solution
A memory system with multiple repair analysis circuits and a control circuit that manages fail address storage and transfer across different regions, utilizing selection signals and redundancy check circuits to efficiently analyze and store fail addresses, even when storage capacity is full.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a single repair analysis circuit is used to store fail addresses, then the device complexity is low, but the storage capacity is limited and cannot handle multiple defective cells
Solution Approach 1:
The repair analysis circuit is divided into multiple independent circuits (first repair analysis circuit, second repair analysis circuit, etc.), each capable of storing fail addresses independently. This segmentation increases the total storage capacity while keeping each individual circuit relatively simple in structure.
Solution Approach 2:
A control circuit is introduced as an intermediary to manage the multiple repair analysis circuits. The control circuit receives fail address information, determines which circuits need to store addresses, and coordinates their operations, thereby enabling scalable storage capacity without requiring complex interconnections between all circuits.
2Quantity of substance
If multiple repair analysis circuits are used to increase storage capacity, then more fail addresses can be stored, but the device complexity increases
Solution Approach 1:
The control circuit is designed with multi-functional capabilities: it can generate control signals for different repair analysis circuits, manage fail address allocation across multiple circuits, and coordinate operations based on the number of defective cells detected. This universal design reduces the need for separate control mechanisms for each circuit.
Solution Approach 2:
The control circuit pre-configures the repair analysis circuits by assigning specific storage roles to each circuit before operation. When defective cells are detected, the control circuit already has the infrastructure in place to efficiently distribute fail addresses across the appropriate circuits, reducing real-time decision complexity.
3Loss of information
If repair analysis circuits store all fail addresses, then complete defect information is preserved, but the storage capacity is quickly exceeded
Solution Approach 1:
The storage capacity is segmented across multiple repair analysis circuits, each with its own storage resources. This distribution allows the system to preserve complete fail address information by spreading it across multiple storage units rather than relying on a single overloaded circuit.
Solution Approach 2:
The control circuit monitors the storage status of repair analysis circuits and dynamically adjusts the distribution of fail addresses. When one circuit approaches capacity, the control circuit redirects subsequent fail address storage to other available circuits, ensuring complete information preservation while efficiently utilizing available storage capacity.
Data Source
AI summary
A memory may include a first repair analysis circuit suitable for storing an input fail address when the input fail address is different from a fail address which is already stored in the first repair analysis circuit, and outputting the input fail address as a first transfer fail address when a storage capacity of the first repair analysis circuit is full; and a second repair analysis circuit suitable for storing the first transfer fail address when the first transfer fail address is different from a fail address which is already stored in the second repair analysis circuit.