Semiconductor Repair Circuit Fuse Optimization
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Solution Overview
Problem
Semiconductor memory devices require a large number of fuses for storing repair addresses, leading to increased device size and programming time, as each fuse needs to be individually programmed and managed.
Innovation Solution
A repair circuit with a first and second fuse circuit, a determination circuit, and an output circuit that selectively performs positive or negative programming operations on a master fuse and address fuses, allowing for efficient generation and storage of repair addresses based on the number of logic bits in the repair address, thereby reducing the number of fuses and programming time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of fuses is increased to store repair addresses, then the repair address storage capability is improved, but the device size increases
Solution Approach 1:
The patent divides the fuse array into multiple groups, where each group corresponds to a bit position in the repair address. Instead of using one large fuse array, the system segments the storage function across multiple smaller groups, each managed by a dedicated fuse circuit. This segmentation allows for more efficient address storage with reduced overall device area.
Solution Approach 2:
The patent introduces a hierarchical structure where fuse circuits are organized in multiple dimensions - groups of fuses are arranged in a matrix pattern with row and column selections. This dimensional organization allows the system to store repair addresses efficiently by selecting fuses along multiple dimensions rather than using a single linear array, thereby reducing the required device area.
2Adaptability or versatility
If the number of fuses to be programmed is increased, then the repair address storage capability is improved, but the program time increases
Solution Approach 1:
The patent performs preliminary actions by pre-organizing fuse circuits into groups with predetermined row and column selections. The system prepares the fuse array structure in advance so that during programming, only specific groups need to be accessed and programmed based on the repair address bits. This preliminary organization significantly reduces the programming time compared to programming all fuses sequentially.
Solution Approach 2:
Instead of programming all fuses in the array, the system performs partial programming by only activating and programming the specific fuse groups corresponding to the current repair address bits being programmed. This partial action approach reduces the programming time while maintaining the full repair address storage capability.
3Measurement precision
If each fuse is individually programmed and managed, then the repair address storage accuracy is improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple individual fuse management functions into integrated fuse circuits that operate as unified units. Each fuse circuit manages a group of fuses corresponding to a bit position, combining the management of multiple fuses into a single functional unit. This merging reduces device complexity while maintaining accurate repair address storage through systematic group management.
Data Source
AI summary
A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.