Repair Control Circuit for Semiconductor Integrated Circuits
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in reducing test time after cell defect repairs, as simultaneous activation of word lines leads to column repair errors due to incorrect selection signals, preventing the use of methods that reduce testing time.
Innovation Solution
A repair control circuit with a selection signal generation unit, selection unit, and repair address generation unit that generates and compares surplus addresses to determine correct memory block selection signals, allowing simultaneous activation of word lines post-repair, ensuring accurate repair column selection signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If multiple word lines are simultaneously activated to reduce test time, then test time is reduced, but column repair errors occur due to incorrect selection signals
Solution Approach 1:
The repair control circuit performs preliminary actions by generating repair column addresses in advance based on the activated word line information before the actual column selection occurs. This allows the system to pre-calculate the correct repair column selection signals, ensuring accuracy even when multiple word lines are activated simultaneously during testing.
2Reliability
If repair column selection signals are generated based on single word line activation, then column repair accuracy is maintained, but test time cannot be reduced
Solution Approach 1:
The repair control circuit dynamically adapts its operation based on the activation state of word lines. When multiple word lines are activated, the circuit generates corresponding MAT selection signals and calculates repair column addresses dynamically, allowing the system to maintain column repair accuracy while supporting simultaneous word line activation for reduced test time.
3Productivity
If multiple MAT selection signals are simultaneously generated, then word line parallel processing is enabled, but column selection signals are incorrectly activated
Solution Approach 1:
The repair control circuit introduces an intermediary mechanism that receives MAT selection signals from multiple activated word lines and processes them through a coordinated logic system. This intermediary structure ensures that even when multiple MAT selection signals are generated simultaneously, the corresponding column selection signals are correctly activated by using the word line activation information to calculate the appropriate repair column addresses.
Data Source
AI summary
A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses.