Repair Latch Memory Circuit for Soft-Error Recovery
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Solution Overview
Problem
The increasing integration of semiconductor memory systems leads to higher chances of defective memory cells, making it difficult to fabricate memories without any defects, and existing repair mechanisms are prone to errors due to soft errors in latch circuits.
Innovation Solution
A memory system with a nonvolatile memory circuit storing repair information, a repair latch circuit, and a repair circuit that performs boot-up operations during initial and subsequent periods to update data, reducing errors by periodically updating data in latch circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of repair
If repair mechanisms use latch circuits to store repair information, then repair operations can be performed, but soft errors occur in the latch circuits causing repair failures
Solution Approach 1:
The patent creates a copy of the repair information storage function by implementing both a latch circuit (for active storage during operation) and a non-volatile memory circuit (for persistent storage). The non-volatile memory circuit serves as a backup copy that can be read to restore latch circuit contents if soft errors occur, thereby maintaining repair accuracy while preserving the ease of repair through the latch circuit mechanism.
Solution Approach 2:
The patent applies prior cushioning by pre-storing repair information in the non-volatile memory circuit before it is needed for repair operations. This ensures that even if soft errors occur in the latch circuit during normal operation, the repair information is already preserved in the non-volatile memory, providing a safety margin that prevents repair failures.
2Quantity of substance
If memory capacity is increased, then more data can be stored, but the probability of defective memory cells increases
Solution Approach 1:
The patent applies preliminary action by performing boot-up operations during an initial operation period to pre-load and verify repair information in the latch circuit before normal operations begin. This preliminary preparation ensures that repair mechanisms are fully initialized and ready to handle potential defects, allowing the system to achieve high memory capacity while maintaining reliability through proactive defect preparation.
Solution Approach 2:
The patent ensures continuity of useful action by implementing boot-up operations that can be performed multiple times during the memory's operational lifecycle. This continuous verification and update of repair information ensures that the repair mechanism remains effective throughout the memory's operation, allowing high-capacity memory systems to maintain reliability through ongoing maintenance rather than one-time initialization.
3Reliability
If boot-up operation is performed multiple times, then latch circuit errors are reduced, but operation time is consumed
Solution Approach 1:
The patent applies feedback by implementing a control mechanism that determines when boot-up operations should be performed based on detected conditions. The system monitors operational parameters and triggers boot-up operations only when necessary (e.g., after detecting soft errors or during initial startup), rather than performing them continuously. This feedback-driven approach reduces unnecessary boot-up operations and minimizes time loss while maintaining latch circuit accuracy when needed.
Data Source
AI summary
A memory may include a memory array configured to store write data therein and provide the write data stored therein as read data, a nonvolatile memory circuit configured to store repair information therein, a repair latch circuit configured to receive the repair information from the nonvolatile memory circuit and store the received repair information during a boot-up operation, and a repair circuit configured to repair the memory array using the stored repair information of the repair latch circuit, wherein the boot-up operation is performed during an initial operation period of the memory and is performed one or more times thereafter.