Repair Verification Circuit for Memory Redundancy Confirmation
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in accurately verifying whether repair operations for defective memory cells are performed correctly, as malfunctions in repair circuits can hinder precise confirmation of row and column redundancies.
Innovation Solution
A repair verification circuit is introduced, comprising a repair address storage circuit and a redundancy flag generation circuit, which stores repair addresses, compares them with external input addresses, and generates a redundancy flag to confirm the accuracy of repair operations through control signals and output signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a repair operation is performed using a repair circuit to replace defective memory cells with redundant cells, then the functionality of defective memory cells is restored, but it becomes difficult to verify whether the repair operation is performed accurately from outside the semiconductor apparatus
Solution Approach 1:
The patent introduces a verification circuit as an intermediary component between the repair circuit and the external testing environment. This verification circuit includes a verification register that stores verification data and a verification unit that compares repair addresses with stored verification data. The intermediary verification circuit enables external verification of repair operations without requiring direct access to internal repair circuit operations, thus resolving the contradiction between maintaining repair functionality and enabling verification.
Solution Approach 2:
The patent implements a feedback mechanism where the verification unit generates verification results by comparing repair addresses with stored verification data, and these results are output to indicate whether the repair operation was successful. The feedback loop allows the system to confirm whether redundant cells are correctly replacing defective cells, enabling external verification while maintaining the repair operation's integrity.
2Reliability
If repair addresses are stored in an OTP memory circuit, then repair operations can be performed for defective cells, but the test time increases due to the need to confirm repair operation accuracy
Solution Approach 1:
The patent applies preliminary action by pre-storing verification data in the verification register during the manufacturing process, before actual repair operations are needed. The verification data includes expected repair addresses that are prepared in advance. When a repair operation is performed, the verification unit can immediately compare the actual repair address with the pre-stored verification data without requiring time-consuming external verification procedures, thus reducing test time while maintaining reliable repair confirmation.
3Adaptability or versatility
If the repair circuit is designed to replace row and column associations with row and column redundancies, then defective memory cells can be accessed through redundant cells, but the device complexity increases due to additional verification requirements
Solution Approach 1:
The patent segments the verification functionality into distinct modular components: a verification register for storing verification data, a verification unit for comparing addresses, and an output unit for reporting results. This segmentation allows each component to perform its specific function independently, making the overall verification system easier to design, implement, and maintain while supporting comprehensive repair verification for both row and column redundancies.
Data Source
AI summary
A repair verification circuit includes a repair address storage circuit and a redundancy flag generation circuit. The repair address storage circuit stores at least one repair address and generates a comparison result merge signal by comparing the at least one repair address with an external input address. The redundancy flag generation circuit generates a redundancy flag by latching the comparison result merge signal in response to a first control signal generated according to an active command.