Repairable Multi-Layer Memory Chip Stack
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3D chip integration technologies face challenges in efficiently repairing faulty memory elements within a multi-layer memory chip stack without increasing complexity through additional through-silicon-via (TSV) connections or complicated decoder circuits.
Innovation Solution
Incorporating a redundant repair unit with valid, chip ID, and faulty address fields in each memory chip, allowing for cross-layer memory repair without additional TSVs, enabling the data bus to access redundant memory when matching conditions are met, thus enhancing the yield of 3D memory stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 3D chip integration technology is used with existing repair mechanisms, then memory chip repair is limited to within the same layer, but additional TSV connections and complicated decoder circuits are required for cross-layer repair
Solution Approach 1:
The redundant repair unit is designed to serve multiple functions: it can repair faulty memory elements within the same layer and across different layers using the same basic circuit structure. The unit includes a valid field, chip ID field, and redundant memory that can be activated based on match conditions, enabling universal repair capability without requiring separate repair mechanisms for different layers.
Solution Approach 2:
The patent implements repair by creating a copy of the faulty memory data in the redundant repair unit. When a match is found between the chip ID and address fields, the redundant memory containing a copy of the correct data is activated to replace the faulty memory element, eliminating the need for complex physical reconnections.
2Reliability
If redundant repair units are added to each memory chip for cross-layer repair, then repair effectiveness is improved, but hardware cost increases
Solution Approach 1:
The redundant repair unit merges the repair functionality into the existing memory chip structure by utilizing the same data bus and control signals. The unit combines the valid field, chip ID field, and redundant memory in a single integrated block that can be manufactured using standard CMOS processes, reducing additional hardware costs.
Solution Approach 2:
The redundant repair unit performs self-configuration during manufacturing by storing the chip ID and faulty address information in the valid and address fields. This self-service approach eliminates the need for external programming or configuration circuits, reducing hardware complexity and manufacturing cost.
3Measurement precision
If match conditions are set for chip ID and faulty address, then precise repair targeting is achieved, but access control complexity increases
Solution Approach 1:
The chip ID and faulty address information are pre-stored in the valid field and address field of the redundant repair unit during manufacturing. This preliminary action eliminates the need for complex real-time comparison logic during operation, as the match conditions are already configured and can be quickly evaluated using simple equality checks.
Data Source
AI summary
A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.