Repassivation Layer Reduced Opening for Contact Pad Alignment
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Solution Overview
Problem
Semiconductor devices face challenges in achieving precise alignment between contact pads and Redistribution Layers (RDL) due to die shift during encapsulation, limiting the minimum achievable pitch and increasing manufacturing costs in fan-out wafer level chip scale packages (FO-WLCSP).
Innovation Solution
The method involves forming a repassivation layer with a reduced opening over the contact pad, which includes creating a via in an insulating layer over a conductive layer, allowing for improved alignment tolerance by reducing the opening size and enhancing the alignment between contact pads and RDL, thereby addressing the die shift issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a standard opening size is used over the contact pad, then the manufacturing process is simpler, but the alignment tolerance between contact pad and RDL is insufficient due to die shift
Solution Approach 1:
The opening structure is segmented into multiple layers: a first opening in the first insulating layer and a second opening in the repassivation layer. The second opening is smaller than the first opening, creating a nested structure that improves alignment tolerance while maintaining manufacturing feasibility through standard photolithography processes.
Solution Approach 2:
The repassivation layer is formed with a reduced opening specifically over the contact pad area, while the surrounding areas maintain their original structure. This localized modification provides enhanced alignment tolerance only where needed (at the contact pad) without complicating the entire device structure.
2Manufacturing precision
If the opening size is reduced to improve alignment tolerance, then the alignment between contact pad and RDL improves, but the manufacturing complexity increases
Solution Approach 1:
The repassivation layer with the reduced opening is formed in advance during the insulating layer formation process, before the RDL metallization steps. This preliminary action ensures that the alignment tolerance is established early in the manufacturing process, simplifying subsequent steps and eliminating the need for special alignment marks.
3Manufacturing precision
If special alignment marks and metal deposition are used to compensate for die shift, then the alignment tolerance is achieved, but the manufacturing cost increases
Solution Approach 1:
The invention extracts and eliminates the need for special alignment marks and additional metal deposition steps by incorporating the alignment function directly into the repassivation layer structure. The reduced opening in the repassivation layer inherently provides the alignment tolerance, removing unnecessary manufacturing steps and reducing costs.
Data Source
AI summary
A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.