Repeat Pattern Graph Mapping for Faster CGRA Compilation
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Solution Overview
Problem
Existing architectures, such as CPUs and GPUs, face challenges in efficiently executing complex algorithms like deep learning models due to limitations in managing data flow and resource utilization, leading to excessive data transfers and poor hardware utilization.
Innovation Solution
The use of coarse-grained reconfigurable architectures (CGRAs) that allow for programmable dataflow and communication, optimizing computational graphs by mapping and scheduling onto CGRA units based on memory bandwidth, and identifying and assigning repeated patterns to reduce compilation time and enhance runtime performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If coarse-grained reconfigurable architectures are used to improve hardware utilization and reduce data transfer overhead, then productivity and energy efficiency are improved, but device complexity and compilation difficulty increase
Solution Approach 1:
The computational graph is divided into sections that can be independently mapped to CGR units. This segmentation allows the complex architecture to be managed through modular mapping, where each section is handled separately, reducing the overall complexity of the mapping process while maintaining high productivity.
Solution Approach 2:
The system dynamically adjusts mapping parameters based on available memory bandwidth and computational requirements. By changing mapping parameters adaptively, the system optimizes throughput without requiring fixed complex architecture, resolving the contradiction between productivity and device complexity.
2Use of energy by moving object
If computational graphs are optimized by mapping and scheduling onto CGRA units based on memory bandwidth, then productivity and energy efficiency are improved, but compilation time and complexity increase
Solution Approach 1:
Performance information is extracted and mapping decisions are made in advance during compilation, before runtime execution. This preliminary action optimizes energy efficiency by pre-determining the best mapping based on bandwidth availability, reducing runtime overhead while maintaining energy efficiency.
Solution Approach 2:
The system uses configuration data that can be copied and reused for identical computational patterns. When the same computational graph section is mapped multiple times, the configuration can be replicated, reducing compilation time while maintaining optimal energy-efficient mappings.
3Productivity
If repeated patterns in computational graphs are identified and assigned to selected CGR units, then productivity and compilation efficiency are improved, but mapping complexity increases
Solution Approach 1:
Repeated patterns in the computational graph are merged and assigned to the same selected CGR units. This consolidation reduces mapping complexity by treating identical patterns as a single mapping problem, while improving runtime performance through efficient resource reuse.
Solution Approach 2:
The system creates universal mapping configurations that can handle multiple identical computational patterns. A single mapping configuration serves multiple functions by processing repeated patterns, reducing overall mapping complexity while enhancing runtime performance through standardized efficient mappings.
Data Source
AI summary
Techniques and systems disclosed herein relate to optimizing the repeat patten graph mapping for coarse-grained reconfigurable processors. For example, a method of mapping a dataflow graph onto a coarse-grained reconfigurable (CGR) processor including one or more arrays of CGR units may include receiving a dataflow graph of a high-level program and detecting one or more repeated sub-graph patterns within the dataflow graph, each repeated sub-graph pattern comprising a set of operations that recurs across multiple instances in the dataflow graph. The method may then include generating configuration data for the CGR processor including assigning multiple instances of a detected repeated sub-graph pattern to a set of CGR units of the CGR processor.