Repeated Block Routing with Flyover Blockages
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Solution Overview
Problem
In semiconductor chip design, repeated blocks with independent implementations lead to inefficiencies in computation resources, time, debug issues, and verification problems due to differences in timing and layout optimizations, requiring redundant calculations and modifications across multiple instances.
Innovation Solution
Implementing repeated blocks with identical or substantially identical pin placement and flyover blockages to enable global routing, allowing for concurrent optimization and buffer insertion within flyover spaces to streamline chip routing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If repeated blocks are implemented independently with different timing and layout optimizations, then each block instance can be optimized for its specific context, but computational resources and time are significantly increased due to redundant calculations
Solution Approach 1:
The patent merges all repeated block instances into a single master block structure. Instead of independently optimizing each instance, the system creates one master block that represents all instances, and optimizations are performed once on this master block. This eliminates redundant calculations while maintaining the ability to optimize for different timing and layout requirements through a single unified structure.
Solution Approach 2:
The master block structure serves multiple functions simultaneously: it represents all repeated block instances, provides a unified structure for optimizations, and maintains compatibility with different timing and layout requirements. This universal structure allows the system to handle multiple optimization scenarios without requiring separate processing for each instance.
2Manufacturing precision
If each repeated block instance is optimized independently, then specific timing and layout requirements can be met, but the implementation calculations must be redone for each instance
Solution Approach 1:
The system performs all optimization calculations once on the master block structure before deployment. This preliminary action includes determining cell placements, buffer positions, and routing paths for the master block, which then apply to all instances. By performing these calculations in advance on a single structure, the system avoids the need to redo implementations for each individual instance.
3Adaptability or versatility
If repeated blocks are implemented independently, then each instance can be tailored to its specific requirements, but debugging becomes more complex due to differences between instances
Solution Approach 1:
The master block structure maintains local quality by preserving the ability to address specific instance requirements through a unified framework. While the overall structure is standardized, the system can still accommodate different timing and layout optimizations for specific instances by applying localized modifications to the master block structure, thereby simplifying debugging while maintaining adaptability.
4Adaptability or versatility
If independent implementation is used for repeated blocks, then flexibility in optimization is maintained, but verification efforts must be repeated for eachinstance
Solution Approach 1:
The patent merges verification efforts by establishing a single verification process that applies to the master block structure. Instead of verifying each instance separately, the system performs one verification on the unified master block structure, which automatically validates all instances. This significantly reduces verification time while maintaining the flexibility to optimize for different scenarios through the master block framework.
Data Source
AI summary
In various embodiments, each possible different instance of a repeated block can be concurrently modified for chip routing. Repeated blocks can be implemented where all instances of a repeated block are identical or substantially identical. Pin placement may be determined based on analysis of the I/O for all instances. The pin placement may be generated to be identical or substantially similar for all instances. Flyover blockages can be designed into repeated blocks to enable the global router to wire through the repeated block. Buffers and associated pins can be inserted into repeated block within the flyover space where the global router wires to the needed buffer through area pins.