Repeater Chip Extends High-Speed Interconnection Traces
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Solution Overview
Problem
The limited PCB area and high-speed interconnection requirements in multi-path computer systems pose challenges in designing effective multi-node interconnection systems, making it difficult to extend node interconnection traces while meeting design specifications and ensuring reliability and error tolerance.
Innovation Solution
A repeater chip is designed with an interface detecting unit, sequence storing unit, sequence forwarding unit, sequence determining unit, and sequence sorting unit to receive, classify, store, forward, and transmit packet sequences, extending high-speed transmission links and incorporating redundancy and fault detection to improve system availability and error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the length of node interconnection trace is extended to meet high-speed interconnection requirements, then transmission capability is improved, but PCB area consumption increases and design complexity increases
Solution Approach 1:
The patent divides the transmission link into multiple segments by inserting repeater chips between transmission nodes. Each repeater chip handles a shorter transmission segment, allowing the overall link length to be extended without requiring a single long trace that would consume excessive PCB area. The repeater chip breaks the continuous trace into manageable sections.
Solution Approach 2:
The repeater chip acts as an intermediary device between transmission nodes, receiving signals from one node, regenerating them, and forwarding to the next node. This intermediary approach enables extended transmission distances while maintaining signal integrity without requiring proportionally larger PCB area, as the repeater chip consolidates the extension function in a compact form factor.
2Length of moving object
If the length of node interconnection trace is extended, then transmission capability is improved, but hardware design complexity increases
Solution Approach 1:
The repeater chip serves as an intermediary that encapsulates the complexity of signal regeneration and transmission management. By placing this intelligent intermediary device, the system achieves extended transmission capability while the complexity is confined to the repeater chip module itself, rather than distributed throughout the entire interconnection system, thus managing overall hardware design complexity.
Solution Approach 2:
The repeater chip performs self-service functions by automatically detecting link status, regenerating signals, and managing transmission parameters without requiring complex external control logic. This self-service capability reduces the overall hardware design complexity by eliminating the need for additional control circuits and management logic in the host system.
3Reliability
If redundancy links and fault detection links are added to improve system availability, then reliability is improved, but device complexity and PCB area increase
Solution Approach 1:
The patent merges the redundancy link management and fault detection functions into the interface detecting unit of the repeater chip. By combining these reliability-enhancing features within the existing repeater chip structure, the system achieves improved reliability without proportionally increasing overall device complexity, as the additional functions are integrated rather than added as separate external components.
4Productivity
If multiple groups of FIFO storing units are implemented to improve packet processing performance, then processing speed is improved, but device complexity and resource consumption increase
Solution Approach 1:
The patent implements multiple groups of FIFO storing units with different characteristics optimized for different packet types. Each FIFO group is locally optimized for specific packet processing requirements, allowing the system to achieve high overall processing performance by matching the right storage resource to the right packet type, rather than using a single uniform storage solution that would be less efficient.
Data Source
AI summary
A design method of a repeater chip is provided, the repeater chip designed by using the method can implement interconnection among nodes, and implement packet sequence receiving, classifying, storing, forwarding, sorting, and transmitting functions of the repeater chip, thereby implementing effective extension of a high-speed transmission link among the nodes, so as to reduce hardware design difficulties and design risks. The structure of the repeater chip is formed by: an interface detecting unit, a sequence storing unit, a sequence forwarding unit, a sequence determining unit, and a sequence sorting unit.