Replacement Fin Channel Etch for Low-Defect Epitaxial Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in maintaining mobility improvement and short channel control in microelectronic device fabrication, particularly in CMOS transistor devices, is exacerbated by the limitations of traditional trench etch processes that result in faceted trench bottoms, leading to poor epitaxial growth and increased defect densities, which hinder the co-integration of diverse channel materials within the same integrated circuit die.
Innovation Solution
A trench etch methodology using low-energy plasma with ion energy less than 30eV is employed to create non-faceted, low-ion damage trench bottoms, allowing for the deposition of replacement semiconductor materials like SiGe, which reduces defect densities and enhances the interface quality between the substrate and the replacement material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional trench etch processes are used, then trench formation is achieved, but faceted trench bottoms are created leading to poor epitaxial growth and increased defect densities
Solution Approach 1:
The patent changes the energy parameter of the plasma etch process by using low ion energy (less than 30eV) to modify the etching mechanism. This parameter change prevents faceting and ion damage at the trench bottom, enabling high-quality epitaxial growth of replacement channel materials while maintaining trench formation capability
Solution Approach 2:
The patent applies preliminary anti-action by using low ion energy etching to prevent ion damage and faceting before epitaxial growth occurs. This preliminary prevention of harmful effects ensures that the trench bottom is ready for high-quality epitaxial growth without pre-existing defects
2Reliability
If replacement channel materials are deposited to improve mobility, then carrier mobility increases, but defect densities increase due to poor interface quality
Solution Approach 1:
By changing the plasma ion energy parameter to less than 30eV, the patent creates optimal trench bottom conditions that enable high-quality epitaxial growth interfaces. This parameter change allows replacement channel materials to be deposited with low defect densities while maintaining improved carrier mobility
Solution Approach 2:
The patent uses plasma (ionized gas) as the etching medium to achieve precise control over trench bottom morphology. The pneumatic/plasma process allows for low ion energy etching that prevents damage while maintaining etching capability, resulting in superior interfaces for high-mobility channel materials
3Reliability
If diverse channel materials are co-integrated to improve device performance, then transistor performance increases, but process complexity increases
Solution Approach 1:
The low ion energy plasma etch process serves multiple functions: it forms trenches, prevents faceting, reduces ion damage, and prepares surfaces for epitaxial growth. This universal process can be applied to create trenches for various replacement channel materials (SiGe, III-V, etc.) without requiring different etching processes, thereby managing complexity while enabling diverse material integration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in defect-free or low-defect interfaces, enabling higher mobility and improved transistor performance by reducing dislocation and stacking fault counts, thus facilitating the co-integration of diverse channel materials within the same integrated circuit die.
Implementation Method 1
A trench etch methodology using low-energy plasma with ion energy less than 30eV is employed to create non-faceted, low-ion damage trench bottoms
Implementation Method 2
low-energy plasma with ion energy less than 30eV is employed to create non-faceted, low-ion damage trench bottoms
Implementation Method 3
allowing for the deposition of replacement semiconductor materials like SiGe
Data Source
Figure 1
Figure 2a~2b
Figure 2c~2d
AI summary
Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.