Replacement Gate Cavities With Angled Spacers to Prevent Shorting
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes has increased due to the replacement of polysilicon gate electrodes with metal gate electrodes in advanced IC designs, leading to challenges such as shorting and reduced process windows.
Innovation Solution
The use of high k metal gates formed in cavities created by removing polysilicon dummy gates, with a larger process window ensured by sufficient insulation around the dummy gate and the cavity, using a plasma etch process to form spacers with specific angles and depths, and replacing dummy structures with replacement gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon gate electrodes are replaced with metal gate electrodes to improve device performance, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial dummy gates and spacers before the actual gate formation. The dummy gates are created early in the process to define the gate region, and spacers are formed around them to establish precise boundaries. This preliminary structuring simplifies the subsequent metal gate formation by pre-defining the geometry and location, thereby reducing overall process complexity despite the advanced metal gate technology.
Solution Approach 2:
The patent uses dummy gates as intermediary structures that facilitate the transition to metal gate electrodes. These dummy gates serve as temporary placeholders and alignment references during the manufacturing process. They are removed after serving their purpose, allowing the metal gate electrodes to be formed in the precise locations without directly transferring the complexity of metal gate fabrication to earlier process steps.
2Area of moving object
If feature size is decreased to increase functional density, then functional density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate structure formation into distinct modular steps: dummy gate formation, spacer formation around dummy gates, dummy gate removal, and metal gate electrode formation. Each step operates at a manageable scale with clear objectives. The spacer structures segment the process into well-defined regions, allowing precise control at reduced feature sizes without overwhelming process complexity.
Solution Approach 2:
The dummy gates and spacers are formed in advance at the reduced feature sizes, establishing the precise geometry needed for high functional density. This preliminary structuring allows the subsequent metal gate formation to proceed with simplified alignment and deposition processes, thereby achieving high density without proportionally increasing manufacturing complexity.
3Reliability
If dummy gates are removed to form cavities for metal gate electrodes, then device performance is improved, but shorting risk increases
Solution Approach 1:
The patent uses spacers as intermediary protective structures that remain in place during the critical cavity formation and metal gate deposition steps. These spacers act as physical barriers and insulation layers that prevent shorting between adjacent structures. They are positioned precisely around the dummy gates and continue to protect the underlying structures even after dummy gate removal, until they too are selectively removed after serving their protective function.
Solution Approach 2:
The spacers are formed beforehand to provide protective cushioning during the dummy gate removal and metal gate formation processes. They are strategically positioned to prevent direct contact between conductive elements that could cause shorting. This prior protective structuring ensures that the cavity formation process, which inherently carries shorting risk, proceeds safely with built-in protection mechanisms already in place.
4Manufacturing precision
If spacers are formed with specific angles and depths using plasma etch to ensure proper insulation, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The patent replaces complex mechanical alignment and positioning systems with plasma etch processes that self-organize the spacer geometry. The plasma etch method uses chemistry and physics to automatically create the required angles and depths based on the dummy gate and spacer material properties. This substitution of mechanical precision requirements with controllable plasma process parameters simplifies the overall manufacturing system while achieving the needed geometric precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces or prevents shorting and enhances the process window, ensuring reliable fabrication of multi-gate transistors like GAA devices by providing adequate dielectric insulation and precise spacer formation.
Implementation Method 1
removing the second region of the etch stop layer and forming a side edge of the first region of the etch stop layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane
Data Source
AI summary
Provided are devices with replacement structures and methods for fabricating such structures. A method includes forming a layer over a semiconductor material having a top surface in a horizontal plane; forming a dummy structure over the layer, wherein the dummy structure has sidewall, wherein the dummy structure lies directly over a first region of the layer and over a first region of the semiconductor material under the first region of the layer, and wherein the dummy structure does not lie directly over a second region of the layer or over a second region of the semiconductor material under the second region of the layer, and removing the second region of the layer and forming a side edge of the first region of the layer, wherein the side edge forms an angle of from 90 to 100 degrees with the horizontal plane.