Replacement Gate CMP Sequencing for Cap Layer Planarity
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing three-dimensional designs like FinFETs and GAA FETs due to issues such as dishing problems during chemical mechanical polishing (CMP) operations, which affect the planarity and isolation properties of cap insulating layers.
Innovation Solution
A method is introduced to suppress dishing problems during CMP by using specific CMP processes with controlled down forces and slurries, along with precise endpoint detection techniques to ensure planarity and improve the isolation properties of cap insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP operations are used during gate replacement technology, then manufacturing process is simplified, but dishing problems occur that affect planarity and isolation properties
Solution Approach 1:
The CMP process is divided into multiple sequential operations: a first CMP operation to planarize the gate electrode and form a first recess, followed by a second CMP operation to form a second recess and expose the channel region. Each operation uses different down forces and slurry types to address specific planarity requirements at different stages, preventing dishing problems while maintaining manufacturing precision.
Solution Approach 2:
The CMP process employs dynamic adjustment of down force applied to the polishing pad during different stages. A first down force is applied during the first CMP operation, and a second down force is applied during the second CMP operation. This dynamic control allows optimization of material removal rates and prevention of dishing, improving planarity without excessive process complexity.
2Manufacturing precision
If multiple CMP operations with controlled down forces are used, then planarity and isolation properties are improved, but manufacturing process complexity increases
Solution Approach 1:
The isolation formation process is segmented into distinct CMP operations with specific parameters. The first CMP operation focuses on planarizing the gate electrode surface, while the second CMP operation specifically targets forming the recess to expose the channel region. Each operation uses optimized slurry types and down forces to achieve its specific goal, improving isolation properties through targeted processing rather than a single complex operation.
Solution Approach 2:
The CMP process incorporates endpoint detection to monitor when the channel region is exposed during the second CMP operation. This feedback mechanism allows automatic termination of the polishing process at the optimal point, ensuring precise recess depth and preventing over-polishing that would compromise isolation properties, while reducing the need for excessive process margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the planarity and isolation properties of cap insulating layers, reducing manufacturing costs and improving the reliability of FinFET and GAA FET devices.
Implementation Method 1
dishing problems during chemical mechanical polishing (CMP) operations
Data Source
AI summary
In a method of manufacturing a semiconductor device, a sacrificial gate structure is formed over a substrate. The sacrificial gate structure includes a sacrificial gate electrode. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed while a lower portion of the sacrificial gate structure is embedded in the first dielectric layer. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The sacrificial gate electrode is removed.