Self-Aligned Contact Formation in Replacement Gate Devices
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Solution Overview
Problem
The replacement gate process for semiconductor devices, which employs self-aligned contact formation, faces challenges due to multiple chemical mechanical polishing (CMP) operations that introduce gate height variations and reduce process margin, necessitating a more precise and efficient method for forming contacts in transistor devices.
Innovation Solution
The method involves oxidizing an upper portion of the gate metal to form an oxide cap, while maintaining the lower portion metallic, and selectively removing the top region of the oxide cap to expose the source/drain regions for contact formation, thereby avoiding additional CMP operations and reducing gate height variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple CMP operations are performed to planarize gate metal and insulator cap, then device structure is planarized for contact formation, but gate height variation increases and process margin reduces
Solution Approach 1:
The patent extracts the insulator cap material from the gate structure by selectively removing it during contact formation, eliminating the need for a second CMP operation to remove the cap. This reduces the number of planarization steps while maintaining device planarity where needed.
Solution Approach 2:
Instead of adding an insulator cap and then removing it via CMP, the patent inverts the approach by using the gate metal itself as the protective layer during contact formation, eliminating the cap addition-removal cycle entirely.
2Reliability
If insulator cap is deposited on gate metal for protection during contact formation, then gate metal is protected, but additional CMP operation is required increasing process complexity
Solution Approach 1:
The gate metal structure serves multiple functions: as the functional gate electrode and as a protective layer during contact formation. This eliminates the need for a separate insulator cap material, reducing material deposition and removal steps.
Solution Approach 2:
The gate metal structure protects itself during contact formation by maintaining its integrity without requiring an external insulator cap. The process uses the gate metal's inherent properties to prevent damage during subsequent processing steps.
3Manufacturing precision
If multiple planarization operations are performed, then surface flatness is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent eliminates the second CMP operation by extracting the need for an insulator cap removal step. Contact formation proceeds directly after the first CMP planarizes the gate metal surface, reducing total processing time.
Solution Approach 2:
The first CMP operation performs both planarization and prepares the surface for contact formation in one step, eliminating the need for subsequent planarization operations by proper process sequencing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces gate height variability, minimizes the number of processing steps, and integrates oxidation into the manufacturing flow, enhancing the precision and cost-effectiveness of contact formation in transistor devices.
Implementation Method 1
oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap
Data Source
AI summary
A method may include providing a device structure, where the device structure includes a semiconductor region, and a gate structure, disposed over the semiconductor region. The gate structure may further include a gate metal. The method may further include oxidizing an upper portion of the gate metal, wherein the upper portion forms an oxide cap, and wherein a lower portion of the gate metal remains metallic.