Replacement Gate Conductive Feature Structure for Low Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in forming conductive features in advanced transistor structures, such as FinFETs, due to the need for precise control of materials and processes at smaller geometries, which affects production efficiency and costs.
Innovation Solution
The method involves forming conductive features by replacing dummy gate stacks with replacement gate structures, using a combination of deposition and etch processes to create interfacial dielectrics, gate dielectric layers, and conductive fill materials, along with the formation of metal liners and caps to reduce contact resistance and enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If new materials and different materials are used to facilitate scaling down, then device scaling is enabled, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming interfacial dielectrics, depositing gate dielectric layers, creating conductive fill materials, and forming metal liners and caps. Each stage is independently controlled and optimized, allowing complex materials to be processed through manageable segments rather than as a monolithic complex process
Solution Approach 2:
Dummy gate stacks are formed in advance before the actual gate structure is created. These preliminary structures serve as placeholders that guide subsequent processing steps, enabling precise alignment and positioning of the final gate structure without requiring complex real-time control during critical fabrication steps
2Productivity
If device geometry is scaled down, then production efficiency increases and costs decrease, but contact resistance and electrical performance challenges arise
Solution Approach 1:
Multiple material layers are combined to create the conductive feature structure: conductive fill material for low resistance, metal liners for adhesion and barrier properties, and metal caps for surface optimization. This composite approach allows each material to address specific electrical challenges, achieving low contact resistance despite reduced geometry dimensions
Solution Approach 2:
Different regions of the conductive feature are assigned different materials with optimized properties: the conductive fill provides bulk conductivity, the metal liner provides interface quality at critical boundaries, and the metal cap provides surface quality for subsequent connections. This local optimization ensures low contact resistance at each interface while maintaining overall structure integrity at scaled dimensions
Data Source
AI summary
Semiconductor device structure and methods of forming the same are described. The structure includes a dielectric layer disposed over an epitaxy source/drain region and a conductive feature disposed in the dielectric layer. The conductive feature includes a metal liner including a first material and a metal fill surrounded by the metal liner. The metal fill includes the first material having a first grain size. The conductive feature further includes a metal cap disposed on the metal liner and the metal fill, and the metal cap includes the first material having a second grain size different from the first grain size.