Replacement Gate Structure With Convex Cap to Reduce Under-Etching
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining device integrity and performance due to issues such as under-etching of gate structures, which can lead to device defects and reduced reliability.
Innovation Solution
The method involves replacing a dummy gate structure with a replacement gate structure, etching back the replacement gate structure, and depositing an etch barrier with a greater thickness over the center, followed by a conductive cap formation, which results in a flat or convex top surface. This process reduces under-etching and improves the distance between the gate structure and source/drain contacts, enhancing device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure is etched back to form a recess, then the device can accommodate higher capacitance and improved performance, but under-etching occurs leading to device defects and reduced reliability
Solution Approach 1:
An etch barrier layer is deposited over the gate structure before the etch back process. This preliminary action prevents the etch chemistry from attacking the gate structure, ensuring complete and precise etching of the recess without under-etching, thereby eliminating device defects and improving reliability
Solution Approach 2:
The etch barrier layer acts as an intermediary between the etch chemistry and the gate structure. It selectively protects the gate structure during the etch back process, allowing the recess to be formed with high precision without damaging the gate, thus resolving the contradiction between manufacturing precision and device reliability
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise that reduce device integrity and performance
Solution Approach 1:
The invention changes the physical and chemical parameters of the etching process by introducing an etch barrier layer with specific material properties that are selective to the gate structure. This allows precise control of the etching process at reduced feature sizes, maintaining device integrity while enabling higher integration density
Solution Approach 2:
The etch barrier layer is applied locally and selectively to protect specific regions of the gate structure during etching. This localized protection ensures that the etching process maintains precision and integrity even as feature sizes are reduced to increase integration density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The improved gate structure design reduces device defects and enhances performance by minimizing under-etching and increasing the bridge window between the gate and source/drain contacts, leading to more reliable semiconductor devices.
Implementation Method 1
depositing an etch barrier with a greater thickness over the center
Implementation Method 2
depositing an etch barrier with a greater thickness over the center, followed by a conductive cap formation
Data Source
AI summary
Improved gate structures, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a gate structure over a semiconductor substrate, the gate structure including a high-k dielectric layer; a gate electrode over the high-k dielectric layer; a conductive cap over and in contact with the high-k dielectric layer and the gate electrode, a top surface of the conductive cap being convex; and first gate spacers on opposite sides of the gate structure, the high-k dielectric layer and the conductive cap extending between opposite sidewalls of the first gate spacers.