Replacement Gate Structures with Metal–Fluorine Dipole Layers
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in improving integration density, reducing threshold voltage, interface trap density, and minimizing gate leakage.
Innovation Solution
Formation of a dipole layer comprising metal atoms over an interfacial layer, followed by a fluorine incorporation process and anneal to drive metal and fluorine atoms into the interfacial layer, enhancing the threshold voltage and reducing interface trap density while minimizing gate leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but threshold voltage control deteriorates and interface trap density increases
Solution Approach 1:
The patent applies local quality by creating a dipole layer with specific metal atoms (such as aluminum, gallium, or indium) at the interface between the semiconductor channel and the gate dielectric. This localized modification of the interface region provides precise control over threshold voltage without affecting the overall device scaling, thereby maintaining reliability while enabling continued miniaturization for higher integration density.
Solution Approach 2:
The patent utilizes parameter changes by adjusting the composition, thickness, and atomic structure of the dipole layer to independently control threshold voltage, interface trap density, and gate leakage characteristics. By varying these parameters of the dipole layer, the invention enables fine-tuning of device electrical properties decoupled from the minimum feature size, resolving the contradiction between scaling and voltage control.
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but interface trap density increases
Solution Approach 1:
The dipole layer is formed specifically at the critical semiconductor-dielectric interface region, providing localized passivation of interface traps. This targeted approach improves interface quality without requiring changes to the bulk material properties or overall device geometry, enabling continued scaling while maintaining low interface trap density.
Solution Approach 2:
The patent employs composite material structures by combining the dipole layer (containing metal atoms) with the gate dielectric layer to create a multi-layered interface structure. This composite approach leverages the beneficial properties of both materials: the dipole layer provides interface trap passivation and threshold voltage control, while the gate dielectric provides electrical insulation and gate capacitance, together achieving low interface trap density at scaled dimensions.
3Ease of manufacture
If conventional gate structures are used in scaled devices, then manufacturing process remains simple, but gate leakage increases
Solution Approach 1:
The dipole layer is formed preliminarily during the gate stack fabrication process, before final gate electrode deposition. This preliminary action of creating the dipole layer at the interface ensures that threshold voltage control and gate leakage suppression are built into the structure from the outset, rather than requiring additional correction steps later, thereby maintaining manufacturing simplicity while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves threshold voltage, reduces interface trap density, and minimizes gate leakage in semiconductor devices, thereby enhancing device performance and reliability.
Implementation Method 1
Formation of a dipole layer comprising metal atoms over an interfacial layer
Implementation Method 2
followed by a fluorine incorporation process
Implementation Method 3
anneal to drive metal and fluorine atoms into the interfacial layer
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.