Replacement Gate Channel Structure With Dual Inner Spacers
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in controlling the shape and dimensions of nanostructures, which affect the electrical properties and uniformity of nanostructure devices, and there is a need to improve etching resistance and lower capacitance.
Innovation Solution
The atomic concentration of elements like Ge in sacrificial layers is controlled to shape and dimension replacement gate structures and channel regions, and multiple spacer layers are used to enhance etching resistance and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but controlling the shape and dimensions of nanostructures becomes more difficult
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple components: a sacrificial layer, channel layers, and a replacement gate structure. This segmentation allows independent control of each component's formation and removal, enabling precise dimensional control even at reduced feature sizes. The sacrificial layer is patterned first, then channel layers are formed around it, and finally the replacement gate is formed after sacrificial layer removal, with each step contributing to the final precise dimensions.
Solution Approach 2:
The patent utilizes parameter changes by controlling the atomic concentration of semiconductor elements (such as germanium) in the sacrificial and channel layers. By adjusting composition parameters during epitaxial growth, the patent achieves precise control over etch rates and material properties, which directly influences the final shape and dimensions of the nanostructures. This compositional control is critical for maintaining manufacturing precision at smaller feature sizes.
2Device complexity
If conventional single-layer spacer structures are used, then the device structure is simpler, but etching resistance is insufficient
Solution Approach 1:
The patent applies composite materials by forming a multi-layer spacer structure consisting of different material layers with distinct properties. The spacer structure includes a first spacer layer and a second spacer layer with different compositions, where each layer provides specific functionality. This composite structure enhances overall etching resistance while maintaining reasonable device complexity, as the layered approach allows optimization for different etching conditions.
Solution Approach 2:
The patent transitions from a single-layer spacer to a multi-layer spacer structure, adding the dimension of layering. This dimensional change in the spacer architecture provides enhanced etching resistance through the cumulative effect of multiple layers, each contributing to the overall protective function during subsequent etching processes.
3Device complexity
If conventional gate structures are used, then the manufacturing process is simpler, but electrical properties and uniformity are degraded
Solution Approach 1:
The patent applies preliminary action by forming the channel layers around the sacrificial layer before the replacement gate is created. This sequence allows the channel layers to be precisely positioned and shaped in advance, ensuring uniform thickness and composition. The sacrificial layer serves as a template that pre-defines the channel region geometry, which is then preserved when the replacement gate is formed, leading to improved electrical uniformity.
Solution Approach 2:
The patent applies local quality by creating distinct regions with different material compositions: the sacrificial layer has a specific semiconductor element concentration, the channel layers have different concentrations optimized for electrical performance, and the replacement gate has yet another composition. This spatial variation in material properties throughout the gate structure enables optimization of electrical characteristics while managing device complexity.
Data Source
AI summary
An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.