Replacement Gate Cutting to Preserve Fin Stress in FinFETs
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Solution Overview
Problem
In the semiconductor industry, particularly for FinFET devices, existing methods face challenges in maintaining stress in semiconductor fins during processing, which can lead to reduced performance and increased complexity due to stress relaxation and dimensional losses during gate and fin cutting processes.
Innovation Solution
The proposed solution involves cutting gate structures and fins after forming a replacement gate structure, which increases the process window and allows for stress retention in the fins by avoiding the relaxation of stress in the fin, thereby enhancing performance and control in devices at technology nodes of 5 nm and smaller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate and fin cutting processes are performed early in fabrication, then manufacturing complexity is reduced, but stress in the fins is relaxed leading to reduced device performance
Solution Approach 1:
The patent applies preliminary action by performing the gate and fin cutting operations early in the fabrication process, before the stress relaxation issue occurs. By establishing the final gate and fin structures early, the patent maintains stress integrity throughout subsequent processing steps, thereby resolving the contradiction between manufacturing simplicity and device performance
2Manufacturing precision
If replacement gate structure is formed before cutting, then process window is increased and stress is retained, but manufacturing steps are increased
Solution Approach 1:
The patent forms the replacement gate structure as a preliminary step before performing the cutting operations. This preliminary formation of the gate structure establishes a robust framework that maintains stress integrity during subsequent fin cutting, thereby increasing the process window and manufacturing precision despite the additional manufacturing step
Data Source
AI summary
Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.