Replacement Gate Channel Interface Using a Ge-Free Protection Layer
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Solution Overview
Problem
Current semiconductor devices face challenges in improving drive currents and interfacial issues between semiconductive channel regions and gate structures, particularly in FinFETs, due to the limitations of germanium-containing materials.
Innovation Solution
The implementation of a Ge-free semiconductive protection layer between the semiconductive channel region and the gate structure, utilizing oxidation and annealing processes to purify silicon components and reduce germanium content, thereby enhancing the interfacial properties and mobility of charge carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If germanium-containing materials are used to form channel regions, then electron mobility and hole mobility are improved, but interfacial issues between channel regions and gate structures occur
Solution Approach 1:
A Ge-free semiconductive protection layer is introduced as an intermediary between the germanium-containing channel region and the gate structure. This protection layer serves as a mediator that prevents direct contact between the germanium and the gate, thereby eliminating interfacial issues while preserving the high mobility benefits of germanium in the channel region.
Solution Approach 2:
The channel region is segmented into two distinct parts: a germanium-containing channel portion that provides high carrier mobility, and a Ge-free protection layer portion that interfaces with the gate structure. This segmentation allows each region to fulfill its specific function without compromising the other, resolving the contradiction between mobility enhancement and interfacial quality.
2Power
If germanium-containing materials are used to form channel regions, then drive currents are improved, but interface and bulk traps increase
Solution Approach 1:
The Ge-free semiconductive protection layer acts as a mediator that separates the germanium-containing channel from the gate structure, preventing the formation of interface traps at the germanium-gate interface. This intermediary layer maintains the high drive current capability provided by germanium while eliminating the harmful interface traps that would otherwise form.
3Speed
If germanium-containing materials are used to form channel regions, then hole mobility is improved, but interfacial issues between channel regions and gate structures occur
Solution Approach 1:
The Ge-free semiconductive protection layer serves as an intermediary that enables the use of germanium-containing materials for improving hole mobility in PMOS transistors while preventing interfacial issues. By placing this protection layer between the germanium channel and the gate structure, the beneficial hole mobility enhancement is preserved without the detrimental interfacial effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the interfacial quality, increases electron mobility, and achieves high-speed, low-power semiconductor devices by reducing interface and bulk traps, while ensuring reliable device performance.
Implementation Method 1
an oxidation process is performed to remove germanium atoms in the semiconductive protection layer
Implementation Method 2
an annealing process is performed to evaporate germaniums in the oxidation layer
Data Source
AI summary
A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.