Replacement Gate and Inner Spacer Structure for Nanostructure Uniformity
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Solution Overview
Problem
As semiconductor devices undergo miniaturization, challenges arise in controlling the shape and dimensions of replacement gate and inner spacer structures, affecting the electrical properties and uniformity of nanostructure devices, while also requiring improved etching resistance and reduced capacitance.
Innovation Solution
The atomic concentration of elements like germanium in sacrificial layers is controlled to shape and dimension replacement gate structures and channel regions, and multiple spacer layers are used to enhance etching resistance and lower capacitance in nanostructure devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but controlling the shape and dimensions of replacement gate and inner spacer structures becomes more difficult
Solution Approach 1:
The patent segments the gate structure formation into multiple stages: first forming a dummy gate structure, then forming inner spacers, followed by removing the dummy gate and forming a replacement gate. This segmentation allows each step to be optimized independently, improving shape and dimension control at reduced feature sizes while maintaining high integration density
Solution Approach 2:
The patent performs preliminary actions by forming inner spacers before removing the dummy gate structure. These inner spacers serve as pre-positioned structural elements that guide the subsequent replacement gate formation, ensuring precise shape and dimension control even as feature sizes are reduced to increase integration density
2Productivity
If feature size is reduced to improve integration density, then more components fit in a given area, but etching resistance of spacer structures decreases
Solution Approach 1:
The patent employs composite material structures for inner spacers, combining multiple materials with different etching resistance properties. This allows the spacer structures to maintain adequate etching resistance even as their dimensions are reduced to achieve higher integration density
Solution Approach 2:
Inner spacers are formed as preliminary structures before dummy gate removal. These pre-formed spacers provide structural support and etching resistance during subsequent processing steps, enabling reliable fabrication at reduced feature sizes while maintaining high integration density
3Productivity
If replacement gate structure dimensions are reduced to improve integration density, then more devices can be integrated, but electrical properties and uniformity deteriorate
Solution Approach 1:
The gate formation process is segmented into dummy gate formation, inner spacer formation, dummy gate removal, and replacement gate formation. This segmentation allows precise control of each structure's dimensions and properties, maintaining electrical performance and uniformity even as overall device size is reduced to increase integration density
Solution Approach 2:
Inner spacers are formed as preliminary structures that define the precise geometry for the replacement gate. This preliminary action ensures that even when the final gate dimensions are reduced for higher integration density, the electrical properties and uniformity are maintained through precise geometric control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical properties and uniformity of nanostructure devices by controlling the shape and dimensions of replacement gate and channel regions, while also enhancing etching resistance and reducing capacitance.
Implementation Method 1
etching the patterned multi-layer stack to form a first recess adjacent the first gate stack, the etching including an isotropic etching process
Implementation Method 2
epitaxially growing a first source/drain region in the first recess
Data Source
AI summary
An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.