Replacement Gate Structures With Internally Trimmed Spacers
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Solution Overview
Problem
As transistor devices are scaled down, the physical size of the gate cavity decreases, making it challenging to fit all necessary layers for the replacement gate structure, particularly for NMOS devices, leading to voids or seams that result in suboptimal device performance or rejection.
Innovation Solution
The method involves forming internally trimmed sidewall spacers with a stepped cross-sectional configuration, widening the gate cavities to accommodate additional layers by trimming the spacers internally, allowing for reliable filling and deposition of materials within the gate cavities, thereby facilitating the formation of void-free gate metal structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor devices are scaled down to increase density, then device density and switching speed are improved, but the physical size of the gate cavity decreases making it difficult to fit all necessary layers
Solution Approach 1:
The spacer structure is segmented into multiple portions with different lateral widths at different heights. The first portion has a larger lateral width than the second portion, creating a stepped configuration that provides additional space within the gate cavity to accommodate multiple layers without increasing the overall footprint of the device.
Solution Approach 2:
The solution transitions from a two-dimensional uniform spacer to a three-dimensional stepped spacer structure. By varying the lateral width at different vertical levels, the invention utilizes the vertical dimension to create additional horizontal space within the gate cavity, allowing more layers to be fitted without increasing device area.
2Productivity
If the gate cavity size is reduced due to scaling, then device density increases, but voids or seams form during material deposition leading to suboptimal device performance
Solution Approach 1:
The gate cavity space is segmented into different regions by the stepped spacer portions. The first portion with larger lateral width provides adequate space for complete material deposition without voids, while the second portion with smaller lateral width optimizes the overall device footprint. This segmentation allows each region to be optimized for its specific function.
Solution Approach 2:
The lateral width parameter of the spacer is changed at different vertical levels, creating a stepped configuration. This parameter change allows the spacer to provide both sufficient space for complete layer filling (preventing voids) and reduced overall device size, thereby improving both manufacturing precision and device density.
3Ease of manufacture
If uniformly sized spacers are used in scaled-down transistors, then manufacturing is simpler, but there is insufficient space to accommodate all required layers without voids
Solution Approach 1:
The spacer is divided into multiple segments (first portion and second portion) with different lateral widths. This segmentation can be achieved through selective etching or deposition processes that are extensions of standard manufacturing techniques, maintaining relative simplicity while providing the necessary volume variation to accommodate all required layers.
Solution Approach 2:
Instead of changing the spacer size in the horizontal plane (which would affect device footprint), the invention utilizes the vertical dimension to create different lateral widths at different heights. This approach maintains manufacturing simplicity by using vertical process variation rather than complex lateral patterning.
Data Source
AI summary
A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.