Replacement Gate Structure with Low-K Sidewall Spacer
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Solution Overview
Problem
The shrinking dimensions of transistor devices in integrated circuits pose challenges in forming gate structures using the replacement gate technique, leading to issues such as voids or seams in the gate stack, increased parasitic capacitance, and difficulties in filling small recesses, which affect the performance and reliability of semiconductor devices.
Innovation Solution
The method involves forming a gate structure with a recessed sacrificial gate electrode and sidewall spacers, including a low-k insulating material spacer between high-k spacers, to create a wider gate cavity and reduce parasitic capacitance by using a combination of etching and deposition processes to form a replacement gate structure and cap layer, thereby avoiding the need to fill small recesses and minimizing undesired capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length of FETs is decreased to improve operating speed and increase density, then the switching speed improves, but the separation between source and drain regions decreases making it difficult to inhibit electrical potential effects
Solution Approach 1:
The patent transitions from planar FET structure to FinFET three-dimensional structure, where the channel is formed vertically along the fin height rather than laterally. This dimensional change allows the gate to control the channel from three sides (top and two sidewalls), providing superior electrostatic control and reducing short channel effects even at scaled dimensions.
Solution Approach 2:
The patent employs composite gate structures with high-k dielectric materials (such as hafnium oxide, tantalum oxide) combined with metal gate electrodes. This composite approach enables effective gate control at reduced channel lengths while maintaining electrical performance and reducing leakage current.
2Reliability
If replacement gate technique is used to form gate structures in scaled devices, then gate control is improved, but voids or seams form in the gate stack due to small recess dimensions
Solution Approach 1:
The patent performs preliminary actions by forming mandrels and sidewall spacers before creating the final gate structure. The mandrels are formed with controlled dimensions and positions, and sidewall spacers are deposited conformally to define the gate cavity boundaries, ensuring that the subsequent gate material deposition occurs in a pre-defined, void-free space.
Solution Approach 2:
The patent controls the dimensions and material properties of mandrels and sidewall spacers to optimize the gate cavity geometry. By adjusting the mandel diameter, spacer thickness, and etch selectivity ratios, the process ensures complete filling of the gate cavity without void formation while maintaining precise gate length control.
3Productivity
If device pitch is decreased to increase density, then more devices fit on chip, but parasitic capacitance increases affecting performance
Solution Approach 1:
The patent extracts or removes parasitic capacitance sources by optimizing the gate structure design. The FinFET geometry reduces overlap capacitance between gate and source/drain, and the use of low-k dielectric materials in interlayer structures minimizes coupling capacitance, thereby reducing overall parasitic effects despite increased device density.
4Ease of manufacture
If small recesses are filled to form gate structures, then gate formation is completed, but difficulties arise in filling and voids form
Solution Approach 1:
The patent introduces mandrels as intermediary structures that serve as templates for gate formation. These mandrels are formed with dimensions and materials that facilitate complete and uniform filling with gate materials. The sidewall spacers act as additional intermediaries that define the precise boundaries of the gate cavity, ensuring complete filling without voids while maintaining manufacturing feasibility.
Data Source
AI summary
One method and device disclosed includes, among other things, forming a recessed sacrificial gate electrode having a recessed upper surface, performing at least one second etching process to define recessed sidewall spacers positioned adjacent the recessed sacrificial gate electrode, forming a plurality of sidewall spacers within a gate opening above the recessed sidewall spacers, wherein one of the spacers comprises a low-k insulating material that is positioned laterally between two other spacers and a gate cap layer, removing the recessed sacrificial gate electrode and forming a replacement gate structure in its place.