3D Replacement Gate Electrode Structure for Lower Gate Resistance
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Solution Overview
Problem
The increasing gate resistance in field-effect transistors (FETs) due to continuous gate-length scaling hinders high switching speed and increases power consumption, particularly in applications like 5G wireless networks and RF technologies.
Innovation Solution
The semiconductor device structure incorporates replacement gate structures with unique profiles, including a core gate electrode design that provides greater volume of gate electrode material, reducing gate resistance by forming gate electrodes with different top and bottom critical dimensions and incorporating radially extended sections with curved portions, which are formed through specific etching and filling processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate length is scaled down continuously to achieve denser device layouts, then device density is improved, but gate resistance increases
Solution Approach 1:
The gate electrode is divided into multiple sections with different critical dimensions. The top section has a smaller critical dimension for dense packing, while the bottom section has a larger critical dimension for lower resistance, effectively segmenting the gate structure to resolve the contradiction between density and resistance
Solution Approach 2:
The gate electrode structure transitions from a two-dimensional planar view to a three-dimensional structure with radially extended sections and curved portions. This dimensional change allows the gate to achieve both small top critical dimension and large bottom critical dimension simultaneously, reducing resistance while maintaining density
2Area of moving object
If gate length is scaled down continuously, then device layout density is improved, but switching speed is delayed
Solution Approach 1:
The gate electrode is segmented into top and bottom sections with different critical dimensions. The bottom section's larger critical dimension provides lower resistance for faster charging/discharging of the gate capacitance, thereby improving switching speed while the top section maintains dense layout
Solution Approach 2:
By introducing radial extensions and curved portions in the three-dimensional gate structure, the patent achieves both small top critical dimension (for density) and large bottom critical dimension (for speed), resolving the speed-density tradeoff through dimensional transformation
3Area of moving object
If gate length is scaled down continuously, then device layout density is improved, but power consumption is increased
Solution Approach 1:
The gate electrode is segmented with different critical dimensions in top and bottom sections. The bottom section's larger critical dimension reduces resistance, thereby reducing the power consumption associated with gate charging/discharging operations while the top section maintains layout density
Solution Approach 2:
The three-dimensional gate structure with radial extensions and curved portions enables simultaneous achievement of small top critical dimension (for density) and large bottom critical dimension (for lower power consumption), resolving the density-power consumption contradiction
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first gate electrode, which includes a first section having a slanted sidewall and an imaginary sidewall, a second section extending radially from the imaginary sidewall of the first section, the second section has a curved bottom, and a third section extending downwardly from the first section, wherein the third section has a straight sidewall, and the slanted sidewall of the first section connects the straight sidewall of the third section to the curved bottom of the second section. The semiconductor device structure also includes a first gate dielectric layer in contact with the straight sidewall of the third section and the slanted sidewall of the first section, and a first gate spacer in contact with the first gate dielectric layer and the slanted sidewall of the first section.