Replacement Gate FinFET Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The formation of dummy gate structures in semiconductor devices leads to unintended extensions that increase parasitic capacitance and AC degradation due to high-k dielectric material, affecting electrical properties.
Innovation Solution
A surface modification process is applied to the dummy gate structure, converting exposed portions into a surface modification layer with a lower dielectric constant, which remains after the replacement gate process, preventing unwanted gate structure formation in gaps and reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric material is used in dummy gate structures, then gate insulation performance is improved, but parasitic capacitance increases and AC degradation occurs
Solution Approach 1:
The patent applies different dielectric materials to different regions: high-k dielectric material is used in the gate stack for insulation, while low-k dielectric material is used in the gaps between source/drain regions to reduce parasitic capacitance. This local differentiation resolves the contradiction by optimizing each region's electrical properties according to its specific function.
Solution Approach 2:
The patent introduces a low-k dielectric material as an intermediary substance in the gaps between source/drain regions. This intermediary material prevents the formation of unwanted gate structures and reduces parasitic capacitance, while allowing the high-k dielectric to maintain gate insulation performance.
2Reliability
If dummy gate structures are formed with high-k dielectric material, then gate dielectric performance is enhanced, but unwanted gate structure formation occurs in gaps
Solution Approach 1:
The patent differentiates the dielectric material properties by location: high-k dielectric in the gate stack region for performance, and low-k dielectric in the gap regions to prevent unwanted structure formation. This spatial differentiation eliminates the contradiction.
Solution Approach 2:
The patent converts the potentially harmful effect of gap regions (which can lead to unwanted gate formation) into a beneficial feature by filling them with low-k dielectric material. This transforms the gaps from problem areas into controlled regions that actively prevent defects.
3Ease of manufacture
If standard dummy gate process is used, then manufacturing simplicity is maintained, but leakage current increases due to parasitic capacitance
Solution Approach 1:
The patent merges the dummy gate formation process with the gap filling process by using the same low-k dielectric deposition step for both purposes. This integration maintains manufacturing simplicity while simultaneously reducing leakage current through parasitic capacitance reduction.
Solution Approach 2:
The low-k dielectric layer serves multiple functions: it fills the gaps between source/drain regions, prevents unwanted gate structure formation, and reduces parasitic capacitance. This multi-functionality achieves leakage reduction without adding significant process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current and parasitic capacitance, enhancing the electrical performance of semiconductor devices by maintaining the integrity of the gate structure and improving AC characteristics.
Implementation Method 1
converting the exposed surface of the gate layer into a surface modification layer with a lower dielectric constant
Implementation Method 2
converting the exposed surface of the gate layer into a surface modification layer over the gate layer
Data Source
AI summary
A method includes a number of operations. A semiconductor fin is formed and extends from a substrate. A dummy gate structure is formed across the semiconductor fin. An exposed surface of the gate layer is converted into a surface modification layer over the gate layer. Source/drain regions are formed on the semiconductor fin. The dummy gate structure is removed. A gate structure is formed over the semiconductor fin and extends between the source/drain regions and in the surface modification layer.