Replacement Gate Through Piers for Uniform Memory Cell Thickness
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Solution Overview
Problem
Existing semiconductor manufacturing processes for forming memory cells result in high variability in cell thickness, leading to inconsistent electrical properties and system performance issues.
Innovation Solution
A series of processing steps involving the formation of piers and cavities through a stack of materials, followed by selective removal and replacement of piers, allows for the formation of memory cells with consistent thickness, using compatible materials that maintain system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional semiconductor manufacturing processes are used to form memory cells, then memory cells can be produced, but high variability in cell thickness results leading to inconsistent electrical properties
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming sacrificial piers, creating cavities, depositing memory cell materials, and selectively removing piers. This segmentation allows precise control over memory cell thickness by independently optimizing each process step, thereby improving manufacturing precision and electrical property consistency.
Solution Approach 2:
Sacrificial piers are formed in advance before memory cell material deposition. These pre-positioned piers serve as spacers that define the exact thickness of memory cells during subsequent processing steps, ensuring uniform thickness across the memory array before the piers are removed.
2Ease of manufacture
If processing steps are simplified to reduce manufacturing complexity, then ease of manufacture improves, but control over memory cell thickness variability deteriorates
Solution Approach 1:
Sacrificial piers act as intermediary structures that facilitate precise memory cell formation. These temporary structures enable accurate thickness control during manufacturing and are removed after serving their purpose, providing a simple yet effective mechanism for precision without adding permanent complexity to the final device.
Solution Approach 2:
The process utilizes material property changes - specifically the selective removability of sacrificial pier materials compared to memory cell materials. By choosing materials with distinct chemical or physical properties, the process achieves precise thickness control through straightforward deposition and removal operations rather than complex real-time adjustments.
Data Source
AI summary
Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.