Replacement Gate Planarization for Uniform Polysilicon Heights
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Solution Overview
Problem
In semiconductor IC fabrication, especially at advanced process nodes like 20 nm and 16 nm, maintaining uniform polysilicon gate heights across different areas of a chip is challenging, leading to issues like gate height loading, dielectric residue, and incomplete poly-cut during the replacement-gate process.
Innovation Solution
A method involving the formation of an etch stop layer and inter-layer dielectric layer, followed by chemical mechanical planarization and selective etching processes, ensures near uniform heights of polysilicon gates before replacement, addressing the challenges of gate height variations and residue issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If polysilicon gates are formed in different areas of an IC with different gate lengths and fabrication steps, then device functionality is achieved, but gate height uniformity deteriorates
Solution Approach 1:
The patent applies preliminary action by forming an etch stop layer and inter-layer dielectric layer before the replacement gate process, and performing chemical mechanical planarization to flatten the surface. This prepares the structure in advance to ensure uniform polysilicon gate heights across different IC areas, preventing gate height loading issues and enabling successful subsequent gate replacement operations.
2Device complexity
If replacement gate process is performed without uniform polysilicon gate heights, then process complexity is reduced, but manufacturing defects increase
Solution Approach 1:
The patent implements preliminary actions including forming etch stop layers, inter-layer dielectric layers, and performing chemical mechanical planarization before the replacement gate process. These preparatory steps ensure uniform polysilicon gate heights, preventing manufacturing defects such as gate height loading, dielectric residue, and incomplete poly-cut, thereby maintaining high reliability while keeping the replacement gate process simple.
3Manufacturing precision
If chemical mechanical planarization and selective etching are performed, then gate height uniformity is improved, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the planarization and preparation process into distinct sequential steps: forming etch stop layer, forming inter-layer dielectric layer, performing chemical mechanical planarization, and selective etching. This segmentation allows each step to be optimized independently while maintaining overall process control, achieving gate height uniformity without excessive complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a planar top surface with uniformly heighted polysilicon gates, facilitating subsequent gate replacement processes and improving device performance by eliminating over-etching and residue problems.
Implementation Method 1
performing a chemical mechanical planarization (CMP) process to partially remove the dielectric layer
Implementation Method 2
performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer
Data Source
AI summary
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.