Replacement Gate Spacer Treatment for Void-Free Gate Filling

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, the high aspect ratio of gate cavities in FinFET manufacturing leads to voids and seams during the filling process, causing increased gate resistance and electrical delays.

Innovation Solution

A plasma treatment is applied to the spacer sidewalls of the gate cavity, altering the material composition and allowing for deeper penetration at the top, followed by selective removal to widen the opening, facilitating easier and more complete filling of the gate cavity with gate dielectric and electrode layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the gate cavity is filled with gate dielectric and electrode layers, then the gate structure is formed, but voids and seams are created due to high aspect ratio

Engineering Contradiction:
Improvefilling qualityVSAvoidgate resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A plasma treatment is applied to the spacer sidewalls before filling the gate cavity. This preliminary action modifies the spacer material composition at the sidewalls, creating a tapered profile that facilitates subsequent filling operations and prevents void formation during the deposition of gate dielectric and electrode layers.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The plasma treatment selectively alters the material composition of the spacer sidewalls, creating a non-uniform structure where the top portions have different properties than the bottom portions. This local modification enables better filling characteristics at the critical top regions of the gate cavity while maintaining structural integrity at the base.

Inventive Principle:
Principle #3Local quality

2Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated, but the aspect ratio of gate cavities increases leading to voids and seams

Engineering Contradiction:
Improveintegration densityVSAvoidfilling quality
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The plasma treatment changes the material composition parameter of the spacer sidewalls, transforming the uniform spacer structure into a tapered profile. This parameter modification enables successful filling of high aspect ratio gate cavities that result from reduced minimum feature sizes, thereby maintaining manufacturing precision despite increased integration density requirements.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If the spacer is removed entirely, then the gate cavity is formed, but the opening remains narrow making filling difficult

Engineering Contradiction:
Improvefilling easeVSAvoidprocess steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

Instead of completely removing the spacer, a plasma treatment is applied as a preliminary action to modify the spacer sidewalls. This creates a tapered profile that widens the effective opening for filling operations, making the subsequent deposition of gate materials easier while avoiding the need for additional process steps to completely remove the spacer.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces the formation of voids and seams, improving the performance of the gate structure by reducing resistance and enhancing manufacturing yield.

Implementation Method 1

A plasma treatment is applied to the spacer sidewalls of the gate cavity, altering the material composition and allowing for deeper penetration at the top

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Data Source

PatentUS20250343045A1Replacement Gate Methods That Include Treating Spacers to Widen Gate
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250343045A1 patent drawing
  • US20250343045A1 patent drawing
  • US20250343045A1 patent drawing

AI summary

A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.