Replacement Gate Spacer Widening for Void-Free Gate Filling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, the formation of gate structures with high aspect ratios leads to voids and seams during filling, resulting in increased gate resistance and electrical delays.
Innovation Solution
A treatment process is applied to the spacer sidewalls of the gate cavity, altering the material composition and allowing for a deeper penetration, which is then selectively removed to widen the opening, facilitating easier and more complete filling of the gate cavity with gate dielectric and electrode layers, reducing voids and seams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate cavity is filled with gate dielectric and electrode layers, then the gate structure is formed, but voids and seams are created due to high aspect ratio
Solution Approach 1:
The spacer is treated and widened before the gate cavity filling process. This preliminary widening action creates a larger opening that facilitates complete filling of the high aspect ratio cavity, preventing voids and seams from forming during the subsequent dielectric and electrode layer deposition
Solution Approach 2:
The spacer width is selectively increased at specific locations (the opening region) while maintaining the original spacer structure elsewhere. This localized modification provides targeted improvement in filling accessibility without altering the overall device architecture or requiring complete redesign
2Productivity
If the minimum feature size is reduced to increase integration density, then more components can be integrated, but the gate cavity aspect ratio increases leading to filling defects
Solution Approach 1:
Before filling the gate cavity with dielectric and electrode layers, the spacer is pre-treated and widened to create a larger opening. This preliminary structural modification enables complete filling of high aspect ratio cavities that result from reduced feature sizes, maintaining filling quality despite increased integration density
Solution Approach 2:
The physical dimensions of the spacer are changed by widening the opening through treatment and selective removal. This parameter change in the spacer geometry directly addresses the filling difficulties caused by high aspect ratios in scaled-down devices, allowing complete material deposition without voids or seams
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The widened gate cavity enables improved filling with reduced voids or no voids, enhancing the performance of the semiconductor device by lowering gate resistance and electrical delays.
Implementation Method 1
A treatment process is applied to the spacer sidewalls of the gate cavity, altering the material composition
Data Source
AI summary
A method may include forming a dummy dielectric layer over a substrate, and forming a dummy gate over the dummy dielectric layer. The method may also include forming a first spacer adjacent the dummy gate, and removing the dummy gate to form a cavity, where the cavity is defined at least in part by the first spacer. The method may also include performing a plasma treatment on portions of the first spacer, where the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition. The method may also include etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition, and filling the cavity with conductive materials to form a gate structure.