Replacement Gate Stack Formation for pFET and nFET Transistors
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Solution Overview
Problem
Existing replacement metal gate (RMG) processing for transistors faces challenges in reducing gate resistance in p-type field-effect transistors without affecting n-type transistors or work function metals, particularly due to the incompatibility of chlorine and fluorine in improving negative bias temperature instability (NBTI) and the increased thickness of the inversion layer caused by fluorine penetration.
Innovation Solution
The method involves forming replacement gate stacks for both p-type and n-type field-effect transistors using a chlorine-doped tungsten or pure tungsten as precursors for the gate electrode, eliminating the use of fluorine to improve gate resistance and NBTI performance, while maintaining distinct compositions for each type of transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fluorine (F) is used to improve NBTI by passivating defects in the high-k layer, then NBTI performance is improved, but the deposition of fluorine may penetrate through the wetting layer to react with the high-k layer and interfacial layer, increasing the thickness of the inversion layer and reducing capacitance
Solution Approach 1:
The patent extracts fluorine from the deposition process by using alternative precursors that do not contain fluorine, thereby eliminating the harmful penetration effect while maintaining the beneficial NBTI improvement through other means such as chlorine doping
Solution Approach 2:
The patent introduces chlorine as an intermediary element that can passivate defects in the high-k layer without causing the inversion layer thickness increase that fluorine causes. Chlorine serves as a mediator to achieve defect passivation while avoiding the harmful side effects of fluorine penetration
2Ease of manufacture
If conventional tungsten deposition with nucleation layer and cool fill is used, then complete filling of the gate structure is achieved, but the additional precursor and low temperature processing introduce impurities and reduce tungsten grain size, resulting in higher resistivity
Solution Approach 1:
The patent changes the deposition parameters by using chlorine-doped tungsten precursors and adjusting deposition conditions to achieve complete filling while maintaining low resistivity. The parameter change involves transitioning from conventional multi-step low-temperature deposition to a optimized deposition process with controlled chlorine content and temperature
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the gate resistance and reduces NBTI in integrated circuits by avoiding fluorine use, ensuring optimal performance for both p-type and n-type transistors without increasing the inversion layer thickness.
Implementation Method 1
Chlorine (Cl) and fluorine (F) each have been used to improve negative bias temperature instability (NBTI) by passivating defects in the bandgap of the high-k dielectric layer caused by dangling bonds, or unsatisfied valences
Implementation Method 2
tungsten (W) may be deposited thereover using a precursor of tungsten fluoride (WF6)
Data Source
AI summary
A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.