Replacement Gate Stress Memorization for Electron Mobility
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Solution Overview
Problem
The existing stress memorization techniques used in semiconductor manufacturing are not compatible with the gate-last process, leading to reduced stress memorization effect due to offsetting by the gate conductor in the gate-first process, which diminishes the enhancement of electron and hole mobility.
Innovation Solution
A method combining the replacement gate process with a stress memorization technique, where a tensile stress layer is formed on an n-type field effect transistor, the gate is removed, and the stress is memorized by annealing the source and drain regions, allowing enhanced stress to be concentrated in these regions, improving electron mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate-first process is used with stress memorization technique, then the gate structure is formed early in the process, but the gate conductor offsets the stress introduced by the stress material, diminishing the stress memorization effect
Solution Approach 1:
The patent inverts the conventional gate-first sequence by removing the gate conductor after stress memorization rather than forming it first. The gate dielectric is formed, stress material is deposited and annealed to memorize stress in the source/drain regions, then the gate conductor is removed. This inversion eliminates the offsetting effect and enhances stress memorization while remaining compatible with standard fabrication processes.
2Reliability
If a stress material layer is formed to introduce stress, then stress is applied to improve carrier mobility, but the gate conductor formed previously offsets this stress, reducing the overall effect
Solution Approach 1:
The patent extracts the gate conductor after the stress memorization process has been completed. By removing the gate conductor that was previously offsetting the stress, the full stress effect is preserved and concentrated in the source/drain regions. The gate dielectric remains to provide electrical isolation, while the harmful offsetting effect of the gate conductor is eliminated.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stress memorization effect, improving the overall properties of the semiconductor structure by concentrating stress in the source/drain regions, thereby increasing electron mobility and improving the semiconductor's performance.
Implementation Method 1
annealing so that the source region and the drain region memorize a stress induced by the stress layer
Data Source
AI summary
A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer on the n-type field effect transistor; removing the first gate so as to form a gate opening; performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; forming a second gate; removing the tensile stress layer; and forming an interlayer dielectric layer on the n-type field effect transistor. A replacement process is combined with a stress memorization technique for enhancing the stress memorization effect and increasing mobility of electrons, which in turn improves overall properties of the semiconductor structure.