Replacement Gate Passivation for MOS Trap Defect Reduction
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Solution Overview
Problem
Current techniques for improving threshold voltage stability and mitigating leakage current in semiconductor devices, such as MOS transistors, are inadequate, leading to instability and performance degradation due to trap defects in the dielectric and silicon materials.
Innovation Solution
A passivation scheme is introduced using trap-repairing elements like nitrogen, fluorine, and hydrogen to terminate trap defects in the dielectric and silicon materials, thereby enhancing the charging and discharging characteristics of carriers and reducing threshold voltage instability and device noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional techniques are used to improve threshold voltage stability and mitigate leakage current, then device performance is partially improved, but trap defects in dielectric and silicon materials remain, leading to instability and performance degradation
Solution Approach 1:
The patent applies trap-repairing elements (nitrogen, fluorine, hydrogen) that selectively bond to trap defect sites in the dielectric and silicon materials, converting the harmful trap defects into beneficial passivated sites. This approach transforms the harmful effect of trap defects into a benefit by using controlled chemical reactions to eliminate them, thereby improving threshold voltage stability and reducing leakage current without compromising device performance
Solution Approach 2:
The patent modifies the chemical composition parameters of the dielectric and silicon materials by introducing trap-repairing elements during or after fabrication. By changing the elemental composition (adding nitrogen, fluorine, or hydrogen), the electrical properties of the materials are improved, reducing trap density and enhancing device reliability while maintaining structural integrity
2Adaptability or versatility
If device size continues to shrink to provide greater functionality, then device functionality is enhanced, but control of threshold voltage stability and mitigation of leakage current becomes more critical and difficult
Solution Approach 1:
The patent applies trap-repairing elements locally at the interface regions and within the channel area where trap defects have the most significant impact on threshold voltage stability. By concentrating the passivation treatment in these critical local regions rather than uniformly throughout the entire device, the patent achieves improved threshold voltage control and reduced leakage current while maintaining the scaled dimensions and enhanced functionality of modern semiconductor devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation scheme effectively diminishes trap defects, improving the stability and performance of MOS transistors by controlling carrier movement and reducing noise, thus enhancing the overall robustness and efficiency of semiconductor devices.
Implementation Method 1
A passivation scheme is introduced using trap-repairing elements like nitrogen, fluorine, and hydrogen to terminate trap defects in the dielectric and silicon materials
Data Source
AI summary
A method of manufacturing a semiconductor device includes: depositing a first dielectric layer and a second dielectric layer over a substrate; forming a dummy gate electrode over the second dielectric layer; forming a gate spacer surrounding the dummy gate electrode; forming lightly-doped source/drain (LDD) regions in the substrate on two sides of the gate spacer; removing the dummy gate electrode and forming a replacement gate; forming an inter-layer dielectric (ILD) layer over the replacement gate; and performing a first treatment by introducing a trap-repairing element into at least one of the gate spacer, the second dielectric layer, the substrate, the LDD regions and the ILD layer.


