Replacement Gates for Transistor Strain Enhancement
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Solution Overview
Problem
Current semiconductor technologies face challenges in enhancing the performance of NMOS and PMOS transistors, as they do not effectively provide the necessary strain in the channel region to improve drive current and overall transistor performance.
Innovation Solution
The introduction of lateral tensile stress in NMOS transistors and lateral compressive stress in PMOS transistors is achieved by using epitaxial source and drain films with different lattice spacing constants, and a tensile or compressive stressor layer, respectively, to enhance channel strain, while also removing portions of the gate structure to increase strain levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate structures are used in transistors, then the device complexity is reduced and manufacturing is easier, but the transistor performance and drive current are insufficient due to lack of channel strain
Solution Approach 1:
The gate structure is segmented into multiple functional layers including a first gate electrode, a second gate electrode, and an intermediate dielectric layer. This segmentation allows each layer to contribute differently to channel strain, enabling independent optimization of NMOS and PMOS transistor performance through separate stressor mechanisms.
Solution Approach 2:
Different regions of the gate structure are designed with locally optimized properties: the first gate electrode provides tensile strain for NMOS channels, while the second gate electrode provides compressive strain for PMOS channels. This local quality differentiation enables simultaneous optimization of both transistor types within the same device structure.
2Productivity
If no strain is applied to the channel region, then the device structure remains simple and manufacturing is easier, but the drive current and transistor performance are limited
Solution Approach 1:
The patent changes the physical parameters of the gate structure by introducing materials with different stress characteristics. The first gate electrode uses materials that induce tensile stress, while the second gate electrode uses materials that induce compressive stress. This parameter change in material properties directly translates to enhanced drive current through improved carrier mobility in the channel region.
3Adaptability or versatility
If a single gate structure is used for both NMOS and PMOS transistors, then the device complexity is reduced, but it cannot provide both tensile strain for NMOS and compressive strain for PMOS simultaneously
Solution Approach 1:
The gate structure is designed as a universal multi-functional unit that can simultaneously provide tensile strain for NMOS transistors and compressive strain for PMOS transistors. The first and second gate electrodes work together in a single integrated structure to deliver opposite strain types to adjacent transistor channels, achieving versatility without requiring separate gate structures for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves transistor performance by increasing drive current through targeted strain application, optimizing the performance of both NMOS and PMOS transistors.
Implementation Method 1
epitaxial source and drain films with different lattice spacing constants
Implementation Method 2
tensile or compressive stressor layer
Data Source
AI summary
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.