Replacement Memory Testing During Live System Operation
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Solution Overview
Problem
Conventional methods for testing and repairing memory failures in high availability nonstop production environments often require disrupting the production system or using different installation environments, leading to inefficiencies and uncertainties in verifying replacement memory components.
Innovation Solution
A method and system that allow concurrent testing and verification of new memory units in a running processor's memory subsystem, using a test pattern and timer to assess the new memory unit's integrity without affecting the production environment, enabling the system to determine if the new memory is good or bad and configure it for use when testing is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write testing is performed on replacement memory DIMMs, then testing thoroughness is improved, but production system availability deteriorates because the entire productive system must be disabled
Solution Approach 1:
The patent segments the memory testing process by isolating the replacement DIMM into a separate testable unit using a dummy processor and dummy memory configuration. This allows the replacement memory to be tested independently without disabling the entire productive system, thus maintaining production availability while enabling thorough testing of the replacement component.
Solution Approach 2:
The patent introduces intermediary components (dummy processor, dummy memory, and test controller) that mediate between the replacement DIMM and the productive system. These intermediaries enable the replacement memory to be tested in isolation while the productive system continues to operate normally, resolving the contradiction between testing thoroughness and system availability.
2Productivity
If background scrubbing techniques are used for memory testing, then production system availability is maintained, but testing capability is limited to single bit error correction and multiple bit error detection only
Solution Approach 1:
The patent segments the testing capability from the productive system operations by creating an isolated test environment. This segmentation enables comprehensive testing (including write tests and various error patterns) on the replacement DIMM without relying on limited background scrubbing techniques, thus improving testing capability while maintaining production availability.
Solution Approach 2:
The test controller acts as an intermediary that provides enhanced testing capabilities to the replacement DIMM without requiring the productive system to be disabled. This intermediary enables write tests and comprehensive error detection that go beyond the limitations of background scrubbing, while the productive system continues to operate.
3Productivity
If replacement memory DIMMs are installed in production environment, then system operational continuity is maintained, but early life failures and contamination issues cannot be detected before affecting production
Solution Approach 1:
The patent performs preliminary testing actions on the replacement DIMM before it is fully integrated into production use. By conducting comprehensive tests including write tests and error pattern injections in an isolated environment, the system identifies early life failures and contamination issues before they can affect production operations.
Solution Approach 2:
The intermediary test environment serves as a buffer between the replacement DIMM and the productive system. This intermediary allows thorough testing to be performed on the replacement memory, detecting reliability issues before they impact production, while the productive system maintains operational continuity.
Data Source
AI summary
Method and system for repairing memory failure in a computer system in one aspect determines one or more test patterns and time duration for testing the new memory unit that replaced a failed memory unit. The test pattern is written to the new memory unit and read from the new memory unit. The read pattern is compared to the test pattern that was used to write. If the read test pattern and the written test pattern doe not match, a further repair action is taken. If they match, writing and reading of the test pattern repeats until the time duration for testing expires. The new memory unit may be configured as available for use when the write and read test completes successfully for the testing time duration.