Replacement Metal Gate CMOS Structure with Titanium Nitride Layers
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Solution Overview
Problem
Current manufacturing processes for replacement metal gate CMOS devices are complex and costly, particularly when scaling down FET devices, and there is a need to simplify these processes while maintaining performance enhancements and reducing gate leakage current and improving thermal stability.
Innovation Solution
The process involves forming CMOS devices with semiconductor substrates having nFET and pFET portions, each with a gate structure comprising a recess filled with conformal high-k dielectric, titanium nitride layers, and a titanium-rich third nitride layer, followed by a titanium aluminum alloy and aluminum or tungsten to fill the recess, simplifying the fabrication while maintaining performance benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used for replacement metal gate CMOS devices, then device performance can be maintained, but the fabrication process becomes complex and costly
Solution Approach 1:
The gate structure is segmented into multiple functional layers: high-k dielectric layer for electrical performance, titanium nitride layers for work function control and barrier properties, and gate metal layers for conductivity. This segmentation allows each layer to be optimized independently while simplifying the overall fabrication process through standardized deposition sequences
Solution Approach 2:
The titanium nitride layers serve multiple functions simultaneously: they act as barrier layers preventing diffusion, provide work function control for both nFET and pFET devices, and serve as adhesion layers between the high-k dielectric and gate metal. This multi-functionality reduces the number of separate process steps needed
2Productivity
If device scaling is pursued to enhance performance and reduce cost, then smaller devices are achieved, but the technology becomes more complex requiring changes in device structures and fabrication methods
Solution Approach 1:
The patent employs high-k dielectric materials with elevated dielectric constants to maintain effective gate control at reduced thicknesses, enabling device scaling without proportionally reducing gate length. The titanium nitride layers are engineered with specific thickness parameters (typically 1-5 nm) to provide adequate barrier and work function control properties at scaled dimensions
Solution Approach 2:
The gate structure uses composite material stacks combining high-k dielectric (e.g., HfO2, SiO2), titanium nitride (TiN), and gate metals (e.g., tungsten, copper). This composite approach allows each material to contribute its optimal properties: high-k for electrical control, TiN for barrier and work function, and gate metal for conductivity, enabling scaled devices to maintain performance
3Reliability
If metal gates and high-k dielectric materials are used to enhance device performance, then performance improvement is achieved, but gate leakage current and thermal stability issues arise
Solution Approach 1:
The titanium nitride layers serve as intermediary barrier layers between the high-k dielectric and gate metal, preventing direct contact and potential diffusion pathways that would cause leakage. These intermediate TiN layers block metal atoms from diffusing into the high-k dielectric and prevent dielectric materials from migrating into the gate metal, thereby reducing gate leakage current and improving thermal stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the fabrication process, reduces gate leakage current, and enhances thermal stability of nFET devices while maintaining performance enhancements, making the process more cost-effective and efficient.
Implementation Method 1
a recess filled with a conformal high-k dielectric on a bottom and a side of the recess
Implementation Method 2
a first titanium nitride layer on the high-k dielectric
Implementation Method 3
a barrier layer on the first titanium nitride layer
Implementation Method 4
a gate metal filling the remainder of the recess
Data Source
AI summary
A CMOS device that includes an nFET portion, a pFET portion and an interlayer dielectric between the nFET portion and pFET portion. The nFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer in direct physical contact with the barrier layer and a gate metal filling the remainder of the recess. The pFET portion has a gate structure having a recess filled with a conformal high-k dielectric, a first titanium nitride layer on the high-k dielectric, a barrier layer on the first titanium nitride layer, a second titanium nitride layer on the barrier layer, a third titanium nitride layer in direct physical contact with the second titanium nitride layer and a gate metal filling the remainder of the recess.