Replacement Metal Gate Structure for CMOS Devices
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Solution Overview
Problem
Current manufacturing processes for replacement metal gate CMOS devices are complex and costly, particularly when scaling down FET devices, and there is a need to simplify these processes while maintaining performance enhancements and reducing gate leakage current and improving thermal stability.
Innovation Solution
A method involving the formation of high-k dielectric layers, dummy gate structures, spacer formation, interlayer dielectric deposition, and sequential deposition of titanium nitride and metal layers to create a replacement metal gate structure for both nFET and pFET portions, simplifying the fabrication process while ensuring performance benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used for replacement metal gate CMOS devices, then device performance can be maintained, but the fabrication process becomes complex and costly
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming dummy gate structures on all devices, selectively removing dummy gates from nFETs only, and separately forming metal gate structures. This segmentation allows independent optimization of each stage and simplifies the overall process control while maintaining device performance.
Solution Approach 2:
Dummy gate structures are formed preliminarily on both nFET and pFET devices before any metal gate formation. This preliminary action establishes a uniform starting point that enables subsequent selective processing of nFETs without affecting pFETs, reducing overall process complexity.
2Productivity
If FET devices are scaled down to enhance performance and reduce cost, then device density increases, but the manufacturing process becomes more complex
Solution Approach 1:
The dummy gate structure serves multiple functions: it provides a placeholder during fabrication, enables selective removal processes, and defines the eventual metal gate location. This multi-functionality reduces the number of separate process steps needed as devices are scaled down, maintaining manufacturing simplicity despite increased device density.
3Reliability
If metal gate structures are formed to reduce gate leakage current, then electrical performance improves, but fabrication complexity increases
Solution Approach 1:
Metal gate structures are formed locally only where needed (in nFET regions) while pFET regions maintain different gate structures. The selective removal of dummy gates from nFETs enables this local differentiation, allowing optimization of gate leakage in nFETs without unnecessarily complicating pFET fabrication.
4Reliability
If high-k dielectric materials are used to enhance device performance, then electrical characteristics improve, but process complexity increases
Solution Approach 1:
The high-k dielectric formation is merged with the dummy gate structure formation process. The dummy gate structures are formed over the high-k dielectric in a single integrated process sequence, eliminating the need for separate high-k dielectric processing steps and reducing overall fabrication complexity while maintaining performance benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method simplifies the fabrication process, reduces gate leakage current, and enhances thermal stability of nFET devices, maintaining performance enhancements while reducing complexity and cost.
Implementation Method 1
forming a high dielectric constant (high-k) dielectric on an nFET portion of the CMOS device and on a pFET portion of the CMOS device
Implementation Method 2
depositing a first layer of titanium nitride into the recesses in contact with the high-k dielectric on the nFET portion and pFET portion
Implementation Method 3
depositing titanium aluminum onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion
Data Source
AI summary
A method of fabricating a replacement metal gate structure for a CMOS device. The method includes forming a dummy gate structure on an nFET portion and a pFET portion of the CMOS device; depositing an interlayer dielectric between the dummy gate structures; removing the dummy gate structures from the nFET portion and the pFET portion, resulting in a recess on the nFET portion and a recess on the pFET portion; depositing a first layer of titanium nitride into the recesses on the nFET portion and pFET portion; removing the first layer of titanium nitride from the nFET portion only; depositing a second layer of titanium nitride into the recesses on the nFET portion and pFET portion; depositing a gate metal onto the second layer of titanium nitride in the recesses on the nFET portion and pFET portion to fill the remainder of the recesses.