Replica-Biased Amplifier Circuit for Low-Noise Low-Power Bandwidth
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Solution Overview
Problem
Current amplifiers require high power to achieve low noise and high bandwidth, leading to increased power consumption, which is inefficient for applications like speech recognition piezo microphones that need noise levels of 1 µV or less and bandwidths of 20 kHz or more.
Innovation Solution
The amplifier design incorporates replica transistors and a bias control circuit to replicate input transistor configurations, adjust input values based on detection voltage or current, and utilize an active load to maintain low noise and high bandwidth with reduced power consumption by minimizing the number of stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a current-reuse amplifier stacks a plurality of transistors to form an amplifier, then current reuse efficiency is improved, but power consumption increases
Solution Approach 1:
The amplifier is segmented into distinct functional blocks: a first amplification path with transistors M1 and M2, a second amplification path with transistors M3 and M4, and a current reuse path with transistors M5 and M6. This segmentation allows current to be reused efficiently across paths while maintaining low power operation by avoiding excessive stacking of transistors in a single path.
2Measurement precision
If higher power is applied to the amplifier, then noise performance is improved, but power consumption increases
Solution Approach 1:
The amplifier maintains continuous low-noise amplification through the current reuse mechanism. The current flowing through transistors M1 and M2 is reused by transistors M5 and M6, ensuring continuous useful action without requiring higher power levels. This continuous current flow maintains low noise performance while avoiding the power consumption increase that would result from simply applying higher power.
3Use of energy by moving object
If the number of stacked transistors is reduced, then power consumption is decreased, but current reuse efficiency is worsened
Solution Approach 1:
The amplifier transitions from a single-dimensional transistor stack to a multi-dimensional current path network. By organizing transistors in parallel paths (first path: M1-M2, second path: M3-M4, current reuse path: M5-M6), the design achieves current reuse efficiency without increasing the stack height in any single dimension. This dimensional reorganization allows current to flow through multiple paths simultaneously, maintaining efficiency while reducing power consumption.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4
AI summary
An amplifier (200) includes: a first input transistor (211) connected to a first input, a first output, and a power source (250) or a ground, a second input transistor (212) connected to a second input, a second output, and the power source (250) or the ground; a first replica transistor (221) connected to the first input, a detection node (260), and the power source (250) or the ground; a second replica transistor (222) connected to the second input, the detection node (250), and the power source (250) or the ground; and a bias transistor (230) connected to a bias voltage (Vbn), the detection node (260), and the power source (250) or the ground.