Replica Bit Cell Readout for Low-Area Neural MAC Circuits
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Solution Overview
Problem
Existing MAC operations in neural networks are inefficient in terms of power consumption and area usage, as seen in memristive crossbar architectures.
Innovation Solution
A MAC computation circuit with a source bit cell block, replica bit cell block, and a readout circuit that adjusts the state of replica bit cells to match the resistance values of the source bit cells, allowing for efficient digital value reading of MAC operation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memristive crossbar architecture is used for MAC operations, then neural network processing can be performed, but power consumption and area usage are excessive
Solution Approach 1:
The crossbar array is divided into multiple bit cell blocks, each handling a portion of the MAC operation. This segmentation allows parallel processing while reducing the power consumption and area of each individual block, resolving the contradiction between processing performance and power consumption
Solution Approach 2:
The patent introduces a third dimension by stacking multiple crossbar arrays vertically and using bit cell blocks that can be selectively activated. This dimensional expansion enables efficient MAC operations with reduced power consumption by only activating necessary bit cell blocks rather than the entire array
2Productivity
If memristive crossbar architecture is used for MAC operations, then neural network processing can be performed, but area requirements are excessive
Solution Approach 1:
The crossbar array is segmented into multiple bit cell blocks that can be independently activated. This segmentation reduces the active area required for MAC operations by only enabling the necessary bit cell blocks, thus maintaining processing performance while reducing overall area usage
Solution Approach 2:
The patent implements dynamic activation of bit cell blocks based on computational requirements. By selectively enabling only the bit cell blocks needed for current operations, the effective area usage is reduced while maintaining full neural network processing capability when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces power consumption and area requirements by optimizing the MAC computation process, enhancing the efficiency of neural network operations.
Implementation Method 1
The plurality of source bit cells may be configured to determine resistance values indicating respective partial operation results
Implementation Method 2
the comparator may be configured to compare a composite resistance value of the source bit cell block and a composite resistance value of the replica bit cell block based on a voltage applied to the source bit cell block
Data Source
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AI summary
A multiply-accumulate (MAC) computation circuit includes: a source bit cell block configured to determine a MAC operation result of an input signal based on a plurality of source bit cells; a replica bit cell block comprising a plurality of replica bit cells corresponding to the plurality of source bit cells; and a readout circuit configured to read out a digital value of the MAC operation result using the replica bit cell block.