Replica Buffer Calibration Circuit for High-Clock Impedance Matching
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Solution Overview
Problem
High-frequency external clocks hinder impedance adjustment in output buffers of semiconductor devices, leading to incomplete calibration and discarded adjustment results, especially when the number of adjusting steps during one calibration period becomes insufficient.
Innovation Solution
A calibration circuit with first and second replica buffers, a counter circuit, and latch circuits that allow impedance codes to be fetched into latch circuits even if the impedance of the replica buffers does not reach a predetermined level within the calibration period, enabling continued calibration operations from a previous point and improving impedance accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the external clock frequency is increased to achieve higher data transfer rates, then the productivity is improved, but the number of adjusting steps executable during one calibration period decreases, making it difficult to complete impedance adjustment
Solution Approach 1:
The patent makes the calibration period dynamic by allowing it to extend across multiple external clock cycles when necessary. The calibration period is no longer fixed to a single cycle but can be extended dynamically to accommodate the number of adjusting steps required, ensuring that impedance adjustment can be completed even at high external clock frequencies.
Solution Approach 2:
The patent performs preliminary determination of the number of adjusting steps required before starting the calibration operation. Based on this preliminary assessment, the system pre-calculates the required calibration period duration and prepares the necessary resources, allowing the calibration to proceed smoothly without interruption even at high clock frequencies.
2Device complexity
If the calibration period is fixed to a small number of external clock cycles to maintain timing, then the device complexity is reduced, but the impedance adjustment cannot be completed when external clock frequency is high
Solution Approach 1:
The calibration period is made dynamic rather than fixed. The system automatically extends the calibration period across multiple external clock cycles when the required number of adjusting steps exceeds what can be completed in a single calibration period, ensuring reliable calibration completion without complex manual intervention.
Solution Approach 2:
The system continuously monitors the progress of impedance adjustment during calibration and provides feedback on whether the target impedance has been achieved. Based on this feedback, the calibration period is automatically extended or terminated, ensuring reliable completion while maintaining relatively simple control logic.
3Manufacturing precision
If the number of adjusting steps is increased to improve impedance accuracy, then the manufacturing precision is improved, but the calibration period becomes too long to be executed within one external clock cycle at high frequencies
Solution Approach 1:
The calibration operation is segmented into multiple calibration periods when necessary. Each calibration period executes a portion of the required adjusting steps, and the system continues with additional calibration periods until the target impedance accuracy is achieved, allowing high precision without requiring an excessively long single calibration period.
Solution Approach 2:
The system dynamically adjusts the number of calibration periods and the number of adjusting steps per period based on the external clock frequency and the required impedance accuracy. This dynamic adaptation allows the system to maintain high precision requirements while accommodating varying clock frequencies.
Data Source
AI summary
A method includes issuing a calibration command and performing a calibration operation in response to the calibration command. The calibration operation includes adjusting an impedance of a first replica buffer with updating a first code, the first replica buffer being substantially identical in circuit configuration to one of pull-up and pull-down circuits included in an output buffer, adjusting impedance of a second replica buffer with updating a second code, the second replica buffer being substantially identical in circuit configuration to the other of the pull-up and pull-down circuits included in the output buffer, controlling a first latch circuit to hold the first code when the impedance of the first replica buffer reaches a first level, and controlling a second latch circuit to hold the second code when the impedance of the second replica buffer reaches a second level.