Tunable Replica Circuit Glitch Detection for Overvoltage and Slow Clock
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Solution Overview
Problem
Existing tunable replica circuits (TRCs) are unable to detect overvoltage and underclocking attacks, which can cause data to be latched too early, leading to invalid instructions or addresses being processed by processors, as they are designed to only detect undervoltage and overclocking events.
Innovation Solution
Invert the behavior of the TRC to generate an error when timing is met for overvoltage/underclocking attacks and use two TRCs, one for each type of attack, with calibration to define trip points for normal and error conditions, and invert the output signal for overvoltage/underclocking TRC to detect these events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If analog voltage monitors and analog clock monitors are used to detect overvoltage or slow clock, then detection capability is provided, but silicon area consumption increases and portability becomes difficult
Solution Approach 1:
The patent uses a tunable replica circuit that creates a simplified copy of the critical timing path rather than using complex analog monitoring circuits. This replica circuit replicates the essential timing behavior with minimal silicon area, allowing detection of overvoltage and underclocking conditions without the area penalty of traditional analog monitors
Solution Approach 2:
The patent replaces analog voltage and clock monitoring mechanisms with a digital-based tunable replica circuit approach. Instead of using continuous analog signals and comparators, the system uses discrete digital timing measurements and counter-based detection, significantly reducing silicon area while maintaining detection capability
2Reliability
If traditional TRC is used to detect undervoltage and overclocking events, then detection of these specific attacks is achieved, but detection of overvoltage and underclocking attacks is not possible
Solution Approach 1:
The patent inverts the traditional TRC detection logic to detect overvoltage and underclocking attacks. Instead of triggering an error when timing is violated (as in traditional TRC), the system triggers an error when timing is met too early, which is the opposite condition. This inversion allows the same basic circuit architecture to detect previously undetectable attack vectors
Solution Approach 2:
The patent implements a tunable replica circuit where the delay elements can be dynamically adjusted to match different critical path delays in the design. This dynamic configurability allows the single TRC circuit to adapt to various timing scenarios and detect both traditional and inverted timing violations, providing comprehensive attack detection coverage
3Reliability
If multiple separate monitoring circuits are implemented for different attack types, then comprehensive detection coverage is achieved, but device complexity and silicon area increase
Solution Approach 1:
The patent creates a universal tunable replica circuit that can detect multiple types of attacks (undervoltage, overclocking, overvoltage, underclocking) through a single unified architecture. By making the replica circuit tunable and inverting its output logic, one circuit performs the function of what would traditionally require multiple separate monitoring circuits, significantly reducing overall device complexity
Data Source
AI summary
An apparatus, system, and method for are provided. A device includes a first tunable replica circuit configured to detect an undervoltage and overclocking event, a second tunable replica circuit configured to detect an overvoltage and underclocking event, and a countermeasures component configured to alter a circuit of the device responsive to detection of the undervoltage and overclocking event or the overvoltage and underclocking event.