Replica Delay Control Circuit for Accurate DDR Memory Latency
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Solution Overview
Problem
Existing delay control circuits in semiconductor memory devices face errors in measuring latency due to process, voltage, and temperature variations, especially in wide frequency ranges like DDR3 or DDR4 SDRAM, leading to inaccuracies in signal synchronization.
Innovation Solution
A delay control circuit that includes a delay locked loop, a first delay unit, a first replica delay unit, a delay control unit, a measurement unit, and a latency delay unit, which controls the replica delay amount based on the latency of the driving signal to generate an accurate latency signal, thereby synchronizing internal and external clocks across various frequency ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional delay control circuit is used, then the circuit structure is simple, but measurement precision of latency is degraded due to PVT variations
Solution Approach 1:
The patent creates a replica delay path that copies the structure and characteristics of the actual delay path. By measuring the delay in this replica path under controlled conditions, the system can accurately determine latency values without being affected by PVT variations in the actual signal path. The replica delay unit mirrors the delay characteristics while allowing independent measurement and calibration.
Solution Approach 2:
The patent implements a feedback mechanism where the measured delay values from the replica path are used to adjust and calibrate the delay control. The measurement results feed back to the delay control unit, which modifies the delay settings to compensate for PVT variations, thereby maintaining accurate latency measurement across different operating conditions.
2Adaptability or versatility
If the delay control circuit operates across a wide frequency range, then adaptability is improved, but measurement precision deteriorates due to PVT variations
Solution Approach 1:
The patent employs dynamic delay adjustment mechanisms that adapt to different frequency ranges. The delay control unit can dynamically modify the delay settings based on the operating frequency, ensuring accurate latency measurement across wide frequency ranges. The system transitions between different delay configurations to maintain precision under varying frequency conditions.
Solution Approach 2:
The patent changes physical parameters such as delay amounts and measurement timing based on operating frequency. By adjusting these parameters dynamically according to the frequency range, the system maintains measurement precision across wide frequency variations. The measurement unit adapts its measurement parameters to match the current operating conditions.
3Adaptability or versatility
If the replica delay amount is increased to cover wide frequency ranges, then adaptability is improved, but path information measurement accuracy is degraded
Solution Approach 1:
The patent divides the delay range into multiple segments or stages. Instead of using a single large replica delay unit, the system employs multiple smaller delay units that can be selectively activated based on the frequency range. This segmentation allows accurate measurement in each frequency band while maintaining overall adaptability across wide frequency ranges.
Solution Approach 2:
The patent implements dynamic selection of replica delay amounts based on the operating frequency. The measurement unit dynamically adjusts which replica delay path to use, selecting appropriate delay amounts that match the current frequency range. This dynamic adaptation ensures both wide frequency coverage and high measurement accuracy without being constrained by a fixed large delay amount.
Data Source
AI summary
A delay control circuit includes a delay locked loop configured to delay an external clock by a first delay amount and generate an internal clock, a first delay unit configured to delay an input signal by a first delay amount, a first replica delay unit having a replica delay amount corresponding to a modeled delay amount of a system, a delay control unit configured to control the replica delay amount in response to a latency of an input signal, a measurement unit configured to measure the first delay amount and the controlled replica delay amount and generate path information, an operation unit configured to generate delay information in response to the latency of the input signal and the path information, and a latency delay unit configured to delay the delayed input signal of the first delay unit by the delay information and generate a latency signal.