Replica Delay Control in Phase Quantization Circuits Under PVT Drift
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Solution Overview
Problem
The delay value ratios in conventional phase difference quantization circuits tend to deviate due to variations in PVT (process, voltage, and temperature), leading to inaccurate generation of binary codes representing phase differences between signals.
Innovation Solution
A delay value control circuit is introduced, which includes replica delay units and a delay control unit to compare phases and adjust delay values, maintaining constant ratios between delay units through calibration, ensuring precise phase difference quantization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If delay units are used in phase difference quantization circuit, then phase difference can be quantized into digital codes, but delay value ratios deviate due to PVT variations
Solution Approach 1:
The patent introduces a feedback mechanism where the delay control unit continuously monitors the delay values of multiple delay units and adjusts their delay values to maintain constant ratios. The control unit receives feedback about PVT variations and dynamically compensates for them by adjusting delay values, ensuring that the delay value ratios remain constant despite environmental changes.
Solution Approach 2:
The patent changes the delay values of delay units dynamically based on detected PVT variations. The delay control unit modifies the delay parameters of individual delay units to compensate for ratio deviations caused by process, voltage, and temperature variations, thereby maintaining constant delay value ratios across different operating conditions.
2Measurement precision
If delay value ratios are maintained constant through calibration, then accurate digital codes are generated, but device complexity increases
Solution Approach 1:
The patent introduces a delay control unit as an intermediary component that mediates between the delay units and the phase difference quantization process. This control unit simplifies the overall system by centralizing the complexity of ratio maintenance in a single dedicated component, rather than requiring complex interconnections and control logic across all delay units.
Solution Approach 2:
The patent uses replica delay units that copy the structure and characteristics of the main delay units. These replica units are used for calibration and ratio verification, allowing the system to maintain accurate delay value ratios without requiring complex real-time adjustment mechanisms for each individual delay unit.
3Reliability
If replica delay units are added for calibration, then delay value ratios are maintained, but device complexity increases
Solution Approach 1:
The patent performs calibration using replica delay units before the actual phase difference quantization operation. The delay control unit pre-adjusts the delay values of the delay units to establish correct ratios, and then locks these values during normal operation. This preliminary calibration action eliminates the need for continuous complex adjustments during operation, reducing overall system complexity.
Solution Approach 2:
The patent creates simplified replica delay units that copy the essential characteristics of the main delay units but are optimized for calibration purposes. These replica units provide a straightforward method for verifying and adjusting delay value ratios without requiring the full complexity of the main quantization circuitry, thereby maintaining reliability while controlling complexity.
Data Source
AI summary
A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.