Synthesizable Clock Doubler with Replica Oscillator Duty Correction
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Solution Overview
Problem
Existing clock designs face challenges in achieving optimal performance due to factors such as space constraints and the need for precise clock cycle and duty cycle correction, which are not adequately addressed by current methods.
Innovation Solution
A clock doubler system utilizing a ring oscillator and replica ring oscillators for timing information and programmable delays to correct clock cycle-to-cycle variation and duty cycle, implemented with logic cells from a standard cell library, enabling synthesizable and efficient clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional clock designs are used, then space constraints are reduced, but clock cycle accuracy and duty cycle precision deteriorate
Solution Approach 1:
The patent implements calibration and correction circuits that are integrated within the clock doubler structure itself. The ring oscillator for calibration, delay circuits for correction, and counters for measurement are nested within the main clock generation block, allowing precise clock cycle and duty cycle correction without requiring separate external calibration devices, thus maintaining high manufacturing precision while minimizing space occupation.
Solution Approach 2:
The patent introduces intermediary calibration circuits and delay elements that mediate between the input clock and output clock generation. These intermediary components (ring oscillators, delay circuits, counters) provide the necessary measurement and correction functions without requiring large external calibration equipment, resolving the contradiction between precision and space constraints.
2Measurement precision
If clock cycle correction circuits are added, then clock measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent designs the calibration and correction circuits to serve multiple functions simultaneously. The ring oscillator serves both as a frequency reference and a calibration source. The delay circuits provide both duty cycle correction and phase alignment. The counters perform both measurement and control functions. This multi-functionality reduces the need for separate dedicated circuits, thereby improving measurement precision without proportionally increasing device complexity.
Solution Approach 2:
The patent merges the calibration, measurement, and correction functions into a unified clock doubler architecture. Rather than having separate independent circuits for each function, the design integrates these functions sharing common resources (such as the ring oscillator serving multiple purposes), which reduces overall circuit complexity while maintaining high measurement precision.
3Manufacturing precision
If ring oscillators and delay circuits are implemented, then clock doubling accuracy is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic control of the delay circuits and ring oscillators based on actual clock signal characteristics. The calibration process dynamically adjusts delay values to achieve optimal clock doubling accuracy. This dynamic operation allows the system to achieve high accuracy only when needed during calibration and correction phases, rather than continuously operating at maximum precision level, thereby reducing overall power consumption while maintaining clock doubling accuracy.
Data Source
AI summary
A synthesizable clock doubler is disclosed. The clock doubler is implemented using unique combination of logic cells from a standard cell library. At the core of the clock doubler is a high-frequency ring oscillator that generates timing information for clock measurements. Replica ring oscillators are used to generate programmable delays for the correction of the output clock imperfection, such as cycle-to-cycle variation and duty cycle of the doubled clock.