Replica Circuit Global Reset for Pulse Latch Pre-decoders
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pulse latch based memory pre-decoders are susceptible to unwanted spurious signals, which can affect memory address inputs during hold time requirements, necessitating a robust reset mechanism to prevent spurious data latching across process, voltage, and temperature variations.
Innovation Solution
A global reset generation method using replica circuits that mimic the pulse latch circuit, generating a reset signal to ensure proper latching margins by accommodating worst-case hold pulse delays and operating within the same voltage domain as the pre-decoded memory address output, allowing for effective resetting before the next clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a pulse latch based pre-decoder is used to reduce memory access times, then productivity is improved, but the circuit becomes susceptible to spurious signals during hold time
Solution Approach 1:
The reset signal is generated in advance using a replica latch that mimics the timing characteristics of the actual pulse latch. This preliminary reset action ensures that the latch is properly cleared before new data arrives, preventing spurious signals from being latched while maintaining the fast access times of the pulse latch architecture
2Reliability
If a reset mechanism is added to prevent spurious data latching, then reliability is improved, but device complexity increases
Solution Approach 1:
A replica latch is created as a simplified copy of the actual pulse latch circuit. This replica serves solely to generate the reset signal and does not participate in the main data path, thereby providing the necessary reliability improvement while adding minimal complexity to the overall system
3Adaptability or versatility
If voltage level shifters are used to manage signal levels across different domains, then adaptability is improved, but device complexity increases
Solution Approach 1:
The replica latch circuit generates the reset signal intrinsically from its own internal timing characteristics and voltage domain. This self-service approach eliminates the need for external voltage level shifters or additional signal conditioning circuits, maintaining adaptability while reducing overall device complexity
Data Source
AI summary
A global reset generation method for a pulse latch based pre-decoders in memories that comprises generating a pre-decoded memory address output for a pulse latch circuit, generating a reset signal to reset the pulse latch circuit, providing a combined signal of the pre-decoded memory address output and the reset signal, feeding the combined signal into a low voltage threshold device to manipulate resetting the pulse latch circuit, wherein generating a reset signal comprises generating a reset signal from a matched circuit that is configured to mimic the function of the latch circuit to be reset and wherein generating a reset signal comprises configuring the matched circuit to accommodate a worst case hold pulse delay to allow for resetting the pulse latch before a new clock cycle performs the resetting and having the matched circuit provide the reset signal and a pre-decoded memory address output in the same voltage domain.