Replica Routing for Semiconductor Memory Timing Synchronization
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Solution Overview
Problem
In semiconductor memory devices like DRAM, timing differences occur in the read data reaching the control circuit due to the varying positions of memory cell arrays, leading to inefficiencies.
Innovation Solution
The implementation of bank logic circuits with replica paths for data release signals, which detour through paths with similar wiring lengths to the original paths, reduces timing differences by synchronizing data transfer across memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell arrays are positioned at different locations to increase storage capacity, then the storage capacity is improved, but timing differences in data transfer occur
Solution Approach 1:
The patent segments the data transfer path into two separate paths: a first path for data release signals from memory cell arrays to bank logic circuits, and a second path (replica path) for replica data release signals. This segmentation allows independent optimization of each path to achieve timing synchronization despite different physical distances from memory cell arrays to the control circuit.
Solution Approach 2:
The patent creates a replica path that copies the structure and characteristics of the original data release path. By designing the replica path to have similar wiring length and signal propagation characteristics, the system can use the copied path to generate timing reference signals that compensate for position-dependent timing variations in the original path.
2Loss of time
If timing adjustment circuits are added to synchronize data transfer, then timing differences are reduced, but device complexity increases
Solution Approach 1:
Instead of adding complex timing adjustment circuits to the original data path, the patent creates a separate replica path that copies the essential timing characteristics. This copying approach allows timing synchronization to be achieved through path matching rather than complex active adjustment circuits, thereby reducing overall device complexity.
Solution Approach 2:
The patent designs the replica path to have equivalent electrical characteristics (wiring length, signal propagation delay) to the original data release path. By creating equipotential timing conditions through path matching, the system achieves synchronization without requiring complex timing adjustment circuits, thus reducing device complexity.
Data Source
AI summary
An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.