Memory Timing Drift Detection via Replica Slow-Clock Phase Sensing
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Solution Overview
Problem
Memory systems face timing drift issues due to temperature and voltage variations, causing phase misalignment between timing references in memory devices and controllers, which affects data transport efficiency.
Innovation Solution
A memory system that uses a low-frequency slow clock signal to determine phase delays in the clock distribution circuit of a memory device, allowing for accurate calibration and synchronization of timing signals during power down or drift events, utilizing a drift detection circuit with configurable replica delay elements and phase to digital converters to adjust phase adjustments for optimal data transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-frequency clock signal is used for data transport, then data transfer speed is improved, but timing drift due to temperature and voltage variations increases
Solution Approach 1:
A low-frequency slow clock signal is introduced as an intermediary to carry timing reference information from the memory controller to the memory device. This slow clock signal is less susceptible to timing drift and serves as a stable reference for phase alignment, resolving the contradiction between high-speed data transfer and timing reliability
Solution Approach 2:
The system performs preliminary phase calibration using the slow clock signal before high-speed data transport begins. By pre-synchronizing the timing references between controller and device during initialization or power-up events, the system establishes accurate phase relationships that maintain synchronization throughout high-speed operation
2Reliability
If PLL is activated continuously to maintain clock synchronization, then timing accuracy is improved, but power consumption increases
Solution Approach 1:
Instead of continuous PLL operation, the system uses periodic phase calibration events triggered by power-up or detected timing drift conditions. The slow clock signal enables these periodic synchronization updates without requiring continuous high-power PLL operation, reducing overall power consumption while maintaining timing accuracy when needed
Solution Approach 2:
The memory device uses its own internal clock distribution circuitry and phase detection capabilities to perform self-calibration based on the received slow clock signal. This eliminates the need for continuous external PLL control signals, allowing the system to maintain synchronization with minimal power expenditure from the controller side
3Measurement precision
If complex calibration circuits are used to correct timing drift, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The memory device creates a replica or copy of the received slow clock signal and compares it with its own internal clock distribution. By using this copied reference signal through simple phase detection logic, the system achieves accurate phase alignment without requiring complex calibration circuits, maintaining measurement precision while minimizing device complexity
Data Source
AI summary
A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.