Replicating Test Code in Non-Naturally Aligned Cache Boundaries

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Processor testing tools face challenges in generating test cases that effectively stress various timing scenarios and memory coherency, particularly due to alignment restrictions in memory operations, making it labor-intensive to test different alignment boundaries while preserving necessary boundaries.

Innovation Solution

Replicating test code and test data into a memory cache with non-naturally aligned data boundaries, allowing for efficient testing of processor memory coherency by preserving double word and quad word boundaries, and placing the same cache line from the L2 cache in both L1 instruction and data caches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If test code and test data are replicated into cache memory with non-naturally aligned data boundaries, then test case generation time is reduced and testing efficiency is improved, but preserving alignment boundaries becomes more complex

Engineering Contradiction:
Improvetest case generation efficiencyVSAvoidalignment boundary management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments test data into multiple sections, each with specific alignment characteristics. By dividing test data into segments that can be independently aligned, the system achieves both non-naturally aligned boundaries for efficiency and preserved alignment where needed, resolving the contradiction between generation speed and alignment complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the test data structure are assigned different alignment properties. The patent applies local quality by making specific sections of test data alignable while other sections use non-natural alignment, allowing the system to optimize overall generation efficiency while maintaining alignment integrity where required by processor architecture

Inventive Principle:
Principle #3Local quality

2Reliability

If multiple test cases are generated for multiple alignment boundaries, then comprehensive coverage of alignment scenarios is achieved, but the overhead of generation and simulation increases

Engineering Contradiction:
Improvealignment boundary test coverageVSAvoidtest case generation and simulation overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent creates a universal test data structure that can serve multiple alignment boundary testing purposes simultaneously. By designing test data with embedded alignment characteristics that work across different boundary scenarios, the system achieves comprehensive coverage without requiring separate test cases for each alignment boundary, thus reducing generation and simulation overhead

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses replicated sections of test data that can be copied and placed in different cache locations with different alignments. By copying and repositioning the same test data structure, the system efficiently tests multiple alignment boundaries without the overhead of generating entirely separate test cases for each scenario

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10169180B2Replicating test code and test data into a cache with non-naturally aligned data boundaries
Publication Date: 2019.01.01 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10169180B2 patent drawing
  • US10169180B2 patent drawing
  • US10169180B2 patent drawing

AI summary

Test code and test data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing test code and test data in the non-naturally aligned data boundaries as described herein allows test code and data to be replicated throughout a cache memory while preserving double word and quad word boundaries in segments of the replicated test code and test data. Coherency of the processor memory can be tested when the same cache line from the level two (L2) cache is simultaneously in both the level one (L1) instruction cache and the L1 data cache.