Replicated Dual-Port Cache with Parity Error Correction
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Solution Overview
Problem
Microprocessor caches are prone to alpha-particle soft errors and require error correction due to changing minimum voltage requirements, leading to reliability issues in high uptime server applications, with existing solutions being costly, complex, or inefficient.
Innovation Solution
A dual-ported replicated data cache with error detection and correction capability, using two memory arrays with independent load ports and per-byte parity, allowing for efficient error correction without increasing cache size significantly and maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is implemented in microprocessor caches, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements error correction by replicating cache data across multiple banks and using copy-back mechanisms. When an error is detected in one bank, the system retrieves the correct data from another bank that holds a copy, thereby correcting the error without complex correction algorithms.
Solution Approach 2:
The patent introduces intermediary structures including tag arrays and data arrays that mediate between the processor and cache banks. These intermediaries facilitate error detection and correction by providing additional check bits and enabling cross-validation of data integrity.
2Reliability
If error correction mechanisms are added to caches, then reliability is improved, but area increases
Solution Approach 1:
The patent merges error correction functionality with existing cache structures by integrating check bits into the tag and data arrays. Rather than adding separate correction circuits, the error detection and correction functions are combined with the normal cache operation, using the same memory cells for both data storage and error checking.
Solution Approach 2:
The cache banks are designed to serve multiple functions: normal data storage, error detection, and error correction. The same physical structures are used for both primary operations and reliability functions, eliminating the need for dedicated error correction hardware that would increase area.
3Reliability
If traditional error correction methods are used, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent performs error detection and correction in advance of data access by continuously monitoring cache banks and pre-correcting errors before they affect processor operations. The copy-back mechanism proactively maintains data integrity by continuously synchronizing replicated banks, so errors are corrected before they can degrade performance.
Solution Approach 2:
The error correction mechanism operates continuously in the background without interrupting normal cache operations. The dual-port banks enable simultaneous read and write operations while error checking and correction proceed continuously, ensuring that reliability maintenance does not degrade overall cache throughput.
Data Source
AI summary
A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.