Replicated Logic Blocks for High-Throughput Datapath Pipelines
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Solution Overview
Problem
Increasing the clock speed and throughput of a processor pipeline while minimizing latency and power consumption, as traditional methods face limitations due to the setup and hold time of additional register stages and increased design size and power usage.
Innovation Solution
Implementing a datapath pipeline with replicated logic blocks that operate in parallel and out of phase, using input and output register stages enabled alternately, and a multiplexer to combine outputs, which reduces the effective clock speed within each block and minimizes register stages, thereby increasing clock speed and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional register stages are inserted to split combinational logic into multiple cycles, then clock speed can be increased, but latency increases due to extra clock cycles required
Solution Approach 1:
The pipeline is segmented into multiple parallel logic paths (e.g., two paths for 2x throughput) with replicated logic blocks in each path. Each path processes data independently, allowing the system to achieve higher throughput by processing multiple data streams simultaneously rather than sequentially through a single logic path.
Solution Approach 2:
Input register stages at the start of each logic path are enabled in turn on successive clock cycles in a periodic pattern. For example, in a 2-path pipeline, the first input register is enabled on even cycles while the second is enabled on odd cycles. This periodic enabling reduces the frequency of register activation, minimizing setup and hold time requirements and allowing higher clock speeds.
2Productivity
If more register stages are added to split logic blocks, then throughput increases, but power consumption and design size increase
Solution Approach 1:
Register stages are enabled periodically rather than on every clock cycle. In a 2x throughput pipeline with parallel paths, each input register is activated every other cycle (e.g., path 0 on even cycles, path 1 on odd cycles). This reduces the switching activity and power consumption of the register stages while maintaining the increased throughput provided by parallel processing.
Solution Approach 2:
The pipeline is configured with a single output register stage that is enabled in advance to receive outputs from multiple logic paths. This preliminary configuration allows the system to consolidate outputs from parallel paths efficiently, reducing the total number of register stages needed compared to having separate output registers for each path.
3Speed
If logic is split into multiple cycles with more register stages, then clock speed increases, but the design complexity increases
Solution Approach 1:
Multiple output register stages from different logic paths are merged into a single output register stage. The multiplexer combines outputs from parallel logic paths and feeds them into one shared output register, which is enabled in advance to receive data from any active path. This merging reduces the total number of register stages and simplifies the design while maintaining high clock speeds.
Solution Approach 2:
The single output register stage serves multiple functions by receiving outputs from multiple different logic paths. Instead of having dedicated output registers for each path, one universal output register handles data from all paths, reducing design complexity and component count while supporting the parallel processing architecture.
Data Source
AI summary
A datapath pipeline which uses replicated logic blocks to increase the throughput of the pipeline is described. In an embodiment, the pipeline, or a part thereof, comprises a number of parallel logic paths each comprising the same logic. Input register stages at the start of each logic path are enabled in turn on successive clock cycles such that data is read into each logic path in turn and the logic in the different paths operates out of phase. The output of the logic paths is read into one or more output register stages and the logic paths are combined using a multiplexer which selects an output from one of the logic paths on any clock cycle. Various optimization techniques are described and in various examples, register retiming may also be used. In various examples, the datapath pipeline is within a processor.